drm/i915: Enable DDI IO power domains in the DP MST path

Commit 62b695662a24 ("drm/i915: Only enable DDI IO power domains after
enabling DPLL") changed how the DDI IO power domains get enabled, but
neglected the need to enable those domains when enabling a DP connector
with MST enabled, leading to

    Kernel panic - not syncing: Timeout: Not all CPUs entered broadcast exception handler

Fixes: 62b695662a24 ("drm/i915: Only enable DDI IO power domains after enabling DPLL")
Cc: Imre Deak <[email protected]>
Cc: Ander Conselvan de Oliveira <[email protected]>
Cc: David Weinehall <[email protected]>
Cc: Daniel Vetter <[email protected]>
Cc: Jani Nikula <[email protected]>
Cc: [email protected]
Cc: Ville Syrjälä <[email protected]>
Reported-by: Ville Syrjälä <[email protected]>
Signed-off-by: Ander Conselvan de Oliveira <[email protected]>
Reviewed-by: Imre Deak <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index d94fd4b80963517b1c369c93b835f30ff2eeaaf4..a8334e18c4fc08a5381d600fb1b8d05ce50477ca 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -163,6 +163,9 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
                intel_ddi_clk_select(&intel_dig_port->base,
                                     pipe_config->shared_dpll);
 
+               intel_display_power_get(dev_priv,
+                                       intel_dig_port->ddi_io_power_domain);
+
                intel_prepare_dp_ddi_buffers(&intel_dig_port->base);
                intel_dp_set_link_params(intel_dp,
                                         pipe_config->port_clock,