ipq806x: dts: rework PCIe nodes for Chromium OnHub

- Reuse the bridges node defined on "qcom-ipq8064.dtsi".
- Rename PCIe device nodes to unified "wifi@0,0".
- Add the missing "qcom,ath10k" compatibles.
- Remove unseless property "interrupt-controller". There are no
  consumers use these PCIe devices as interrupt controllers.
- Change bus number from 0 to 1, just like other ipq806x devices.
  The valid PCIe bus range on this platform is 1 - 255.

Signed-off-by: Shiji Yang <[email protected]>
Link: https://github.com/openwrt/openwrt/pull/18989
Signed-off-by: Christian Marangi <[email protected]>

diff --git a/target/linux/ipq806x/files-6.12/arch/arm/boot/dts/qcom/qcom-ipq8064-onhub.dtsi b/target/linux/ipq806x/files-6.12/arch/arm/boot/dts/qcom/qcom-ipq8064-onhub.dtsi
index 08f5a4487c73441e6b261a9f0a7fc1674e9a4b5f..14c12ba053edc2249de32c0757a99d5ca619964c 100644 (file)
--- a/target/linux/ipq806x/files-6.12/arch/arm/boot/dts/qcom/qcom-ipq8064-onhub.dtsi
+++ b/target/linux/ipq806x/files-6.12/arch/arm/boot/dts/qcom/qcom-ipq8064-onhub.dtsi
@@ -452,59 +452,38 @@
 
 &pcie0 {
        status = "okay";
+};
 
-       pcie@0 {
-               reg = <0 0 0 0 0>;
-               #interrupt-cells = <1>;
-               #size-cells = <2>;
-               #address-cells = <3>;
-               device_type = "pci";
-               interrupt-controller;
-
-               ath10k@0,0 {
-                       reg = <0 0 0 0 0>;
-                       device_type = "pci";
-                       qcom,ath10k-sa-gpio = <2 3 4 0>;
-                       qcom,ath10k-sa-gpio-func = <5 5 5 0>;
-               };
+&pcie_bridge0 {
+       wifi@0,0 {
+               compatible = "qcom,ath10k";
+               reg = <0x00010000 0 0 0 0>;
+               qcom,ath10k-sa-gpio = <2 3 4 0>;
+               qcom,ath10k-sa-gpio-func = <5 5 5 0>;
        };
 };
 
 &pcie1 {
        status = "okay";
+};
 
-       pcie@0 {
-               reg = <0 0 0 0 0>;
-               #interrupt-cells = <1>;
-               #size-cells = <2>;
-               #address-cells = <3>;
-               device_type = "pci";
-               interrupt-controller;
-
-               ath10k@0,0 {
-                       reg = <0 0 0 0 0>;
-                       device_type = "pci";
-                       qcom,ath10k-sa-gpio = <2 3 4 0>;
-                       qcom,ath10k-sa-gpio-func = <5 5 5 0>;
-               };
+&pcie_bridge1 {
+       wifi@0,0 {
+               compatible = "qcom,ath10k";
+               reg = <0x00010000 0 0 0 0>;
+               qcom,ath10k-sa-gpio = <2 3 4 0>;
+               qcom,ath10k-sa-gpio-func = <5 5 5 0>;
        };
 };
 
 &pcie2 {
        status = "okay";
+};
 
-       pcie@0 {
-               reg = <0 0 0 0 0>;
-               #interrupt-cells = <1>;
-               #size-cells = <2>;
-               #address-cells = <3>;
-               device_type = "pci";
-               interrupt-controller;
-
-               ath10k@0,0 {
-                       reg = <0 0 0 0 0>;
-                       device_type = "pci";
-               };
+&pcie_bridge2 {
+       wifi@0,0 {
+               compatible = "qcom,ath10k";
+               reg = <0x00010000 0 0 0 0>;
        };
 };