powerpc/bpf: Fix DIVWU instruction opcode

Currently DIVWU stands for *signed* divw opcode:

7d 2a 4b 96 	divwu   r9,r10,r9
7d 2a 4b d6 	divw    r9,r10,r9

Use the *unsigned* divw opcode for DIVWU.

Suggested-by: Vassili Karpov <[email protected]>
Reviewed-by: Vassili Karpov <[email protected]>
Signed-off-by: Vladimir Murzin <[email protected]>
Acked-by: Matt Evans <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 99f87906de1740022c7ee1d6f479740949bead19..3132bb9365f33788771c610aea90e25384f736d0 100644 (file)
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -222,7 +222,7 @@
 #define PPC_INST_MULLW                 0x7c0001d6
 #define PPC_INST_MULHWU                        0x7c000016
 #define PPC_INST_MULLI                 0x1c000000
-#define PPC_INST_DIVWU                 0x7c0003d6
+#define PPC_INST_DIVWU                 0x7c000396
 #define PPC_INST_RLWINM                        0x54000000
 #define PPC_INST_RLDICR                        0x78000004
 #define PPC_INST_SLW                   0x7c000030