This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.
Change-Id: Ib63ef6e2e4616dd56828bfd3800d5fe2df109934
Signed-off-by: Justin Chadwell <[email protected]>
dsb();
/* enable core soft reset */
mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORESRENCR_OFFSET,
- htobe32(1 << 31));
+ htobe32(1U << 31));
dsb();
isb();
/* reset core */
mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORE0_SFT_RST_OFFSET +
- core_pos * 4, htobe32(1 << 31));
+ core_pos * 4, htobe32(1U << 31));
mdelay(10);
}
soc_dev_id == (SVR_LS1043AE << 8)) &&
((val & 0xff) == REV1_1)) {
val = be32toh(mmio_read_32((uintptr_t)gic_align));
- if (val & (1 << GIC_ADDR_BIT)) {
+ if (val & (1U << GIC_ADDR_BIT)) {
*gicc_base = GICC_BASE;
*gicd_base = GICD_BASE;
} else {
#include <stdint.h>
-#define SVR_WO_E 0xFFFFFE
-#define SVR_LS1043A 0x879204
-#define SVR_LS1043AE 0x879200
+#define SVR_WO_E 0xFFFFFEu
+#define SVR_LS1043A 0x879204u
+#define SVR_LS1043AE 0x879200u
void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);