powerpc/64s/idle: avoid POWER9 DD1 and DD2.0 ERAT workaround on DD2.1

DD2.1 does not have to flush the ERAT after a state-loss idle.

Performance testing was done on a DD2.1 using only the stop0 idle state
(the shallowest state which supports state loss), using context_switch
selftest configured to ping-poing between two threads on the same core
and two different cores.

Performance improvement for same core is 7.0%, different cores is 14.8%.

Reviewed-by: Vaidyanathan Srinivasan <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Signed-off-by: Michael Ellerman <[email protected]>

diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S
index 175d49f468af2bcb442794093dc6c2242b0d857f..d77766814090028dda123a396d501ad51e403c27 100644 (file)
--- a/arch/powerpc/kernel/idle_book3s.S
+++ b/arch/powerpc/kernel/idle_book3s.S
@@ -542,7 +542,9 @@ pnv_restore_hyp_resource_arch300:
         * then clear bit 60 in MMCRA to ensure the PMU starts running.
         */
        blt     cr3,1f
+BEGIN_FTR_SECTION
        PPC_INVALIDATE_ERAT
+END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1 | CPU_FTR_POWER9_DD20)
        ld      r1,PACAR1(r13)
        mfspr   r4,SPRN_MMCRA
        ori     r4,r4,(1 << (63-60))