drm/i915: Set PIPECONF color range bit on Valleyview

VLV has the color range selection bit in the PIPECONF register.
Configure it appropriately.

Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Jani Nikula <[email protected]>
[danvet: fixup rebase issues due to slightly different baseline.]
Signed-off-by: Daniel Vetter <[email protected]>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7f860c6b2660f8d2f9c56f91821f90ecd2a98707..b7005640144c291af0e472b439a26da4b2b51aa3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4583,6 +4583,13 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
        else
                pipeconf |= PIPECONF_PROGRESSIVE;
 
+       if (IS_VALLEYVIEW(dev)) {
+               if (intel_crtc->config.limited_color_range)
+                       pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
+               else
+                       pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
+       }
+
        I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
        POSTING_READ(PIPECONF(intel_crtc->pipe));
 }