zynqmp: pm: Correct WDT clock database

WDT used by APU is FPD_WDT. FPD WDT clock is controlled by
FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock
database.

As per FPD_SLCR.WDT_CLK_SEL register, there can be only two
parents of WDT clock not three. Fix the same by correcting it's
parents in clock database.

Signed-off-by: Tejas Patel <[email protected]>
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Acked-by: Jolly Shah <[email protected]>

diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index fefd9ea8fea96b8b37101c0d425702d4610e1ce2..3b3d088c793949a57a1c3585ed08efb0e980aad9 100644 (file)
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -2022,12 +2022,11 @@ static struct pm_clock clocks[] = {
        },
        [CLK_WDT] = {
                .name = "wdt",
-               .control_reg = IOU_SLCR_WDT_CLK_SEL,
+               .control_reg = FPD_SLCR_WDT_CLK_SEL,
                .status_reg = 0,
                .parents = &((int32_t []) {
                        CLK_TOPSW_LSBUS,
                        EXT_CLK_SWDT0 | CLK_EXTERNAL_PARENT,
-                       EXT_CLK_SWDT1 | CLK_EXTERNAL_PARENT,
                        CLK_NA_PARENT
                }),
                .nodes = &wdt_nodes,

diff --git a/plat/xilinx/zynqmp/zynqmp_def.h b/plat/xilinx/zynqmp/zynqmp_def.h
index 8bd75e425007d8264d22badee134e38d00ec9cbc..50fe88aea15e810475c6e70ec3e1f94d51add2e1 100644 (file)
--- a/plat/xilinx/zynqmp/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/zynqmp_def.h
@@ -201,6 +201,7 @@
 #define ACTLR_EL3_L2ACTLR_BIT  (1 << 6)
 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
 
+#define FPD_SLCR_BASEADDR              U(0xFD610000)
 #define IOU_SLCR_BASEADDR              U(0xFF180000)
 
 #define ZYNQMP_RPU_GLBL_CNTL                   U(0xFF9A0000)
@@ -325,7 +326,7 @@
 #define CRL_APB_TIMESTAMP_REF_CTRL     (CRL_APB_CLK_BASE + 0x108)
 #define IOU_SLCR_GEM_CLK_CTRL          (IOU_SLCR_BASEADDR + 0x308)
 #define IOU_SLCR_CAN_MIO_CTRL          (IOU_SLCR_BASEADDR + 0x304)
-#define IOU_SLCR_WDT_CLK_SEL           (IOU_SLCR_BASEADDR + 0x300)
+#define FPD_SLCR_WDT_CLK_SEL           (FPD_SLCR_BASEADDR + 0x100)
 
 /* Global general storage register base address */
 #define GGS_BASEADDR           (0xFFD80030U)