MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.

This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover
MIPSxx-style board cache code.

Signed-off-by: Kevin Cernekee <[email protected]>
Signed-off-by: Ralf Baechle <[email protected]>

diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index b55c2d1b998fee54a905b4cc816d3c7196209673..5ab5fa8c1d8229659a4ba30f204943e5fcf70416 100644 (file)
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -32,6 +32,11 @@ static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
  */
 static void mips_sc_inv(unsigned long addr, unsigned long size)
 {
+       unsigned long lsize = cpu_scache_line_size();
+       unsigned long almask = ~(lsize - 1);
+
+       cache_op(Hit_Writeback_Inv_SD, addr & almask);
+       cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
        blast_inv_scache_range(addr, addr + size);
 }