MIPS: CPS: Read CM GCR base from cop0

Rather than patching the start of mips_cps_core_entry to provide the
base address of the CM GCRs, simply read that base address from the cop0
CMGCRBase register, converting from the physical address to an uncached
virtual address.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Rusty Russell <[email protected]>
Cc: Andrew Bresticker <[email protected]>
Cc: [email protected]
Cc: Niklas Cassel <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Cc: Markos Chandras <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/11203/
Signed-off-by: Ralf Baechle <[email protected]>

diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index b242ae3eb4663e247386f3215034e793a8e054f6..2164dc4deace195fa8abb66879c2e5d03f8b4cf3 100644 (file)
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -67,11 +67,9 @@
 
 LEAF(mips_cps_core_entry)
        /*
-        * These first 12 bytes will be patched by cps_smp_setup to load the
-        * base address of the CM GCRs into register v1 and the CCA to use into
-        * register s0.
+        * These first 4 bytes will be patched by cps_smp_setup to load the
+        * CCA to use into register s0.
         */
-       .quad   0
        .word   0
 
        /* Check whether we're here due to an NMI */
@@ -171,6 +169,12 @@ dcache_done:
        mtc0    t0, CP0_CONFIG
        ehb
 
+       /* Calculate an uncached address for the CM GCRs */
+       MFC0    v1, CP0_CMGCRBASE
+       PTR_SLL v1, v1, 4
+       PTR_LI  t0, UNCAC_BASE
+       PTR_ADDU v1, v1, t0
+
        /* Enter the coherent domain */
        li      t0, 0xff
        sw      t0, GCR_CL_COHERENCE_OFS(v1)

diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index c88937745b4ea18c7faf699f936f00cd42f9372d..8b967507e8520ae772bc23e6fcc2e23ddcea5def 100644 (file)
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -133,11 +133,9 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
        /*
         * Patch the start of mips_cps_core_entry to provide:
         *
-        * v1 = CM base address
         * s0 = kseg0 CCA
         */
        entry_code = (u32 *)&mips_cps_core_entry;
-       UASM_i_LA(&entry_code, 3, (long)mips_cm_base);
        uasm_i_addiu(&entry_code, 16, 0, cca);
        blast_dcache_range((unsigned long)&mips_cps_core_entry,
                           (unsigned long)entry_code);