* In debug builds, we pass a special value in 'arg1' to verify platform
* parameters from BL2 to BL31. In release builds it's not used.
*/
- assert(arg1 == GXBB_BL31_PLAT_PARAM_VAL);
+ assert(arg1 == AML_BL31_PLAT_PARAM_VAL);
/* Check that params passed from BL2 are not NULL. */
from_bl2 = (struct gxbb_bl31_param *) arg0;
/*******************************************************************************
* Platform memory map regions
******************************************************************************/
-#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \
- GXBB_NSDRAM0_SIZE, \
+#define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
+ AML_NSDRAM0_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
-#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \
- GXBB_NSDRAM1_SIZE, \
+#define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
+ AML_NSDRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
-#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \
- GXBB_SEC_DEVICE0_SIZE, \
+#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
+ AML_SEC_DEVICE0_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \
- GXBB_SEC_DEVICE1_SIZE, \
+#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
+ AML_SEC_DEVICE1_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \
- GXBB_TZRAM_SIZE, \
+#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
+ AML_TZRAM_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \
- GXBB_SEC_DEVICE2_SIZE, \
+#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
+ AML_SEC_DEVICE2_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \
- GXBB_SEC_DEVICE3_SIZE, \
+#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
+ AML_SEC_DEVICE3_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
static const mmap_region_t gxbb_mmap[] = {
{
uint32_t val;
- val = mmio_read_32(GXBB_SYS_CPU_CFG7);
+ val = mmio_read_32(AML_SYS_CPU_CFG7);
val &= 0xFDFFFFFF;
- mmio_write_32(GXBB_SYS_CPU_CFG7, val);
+ mmio_write_32(AML_SYS_CPU_CFG7, val);
- val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL);
+ val = mmio_read_32(AML_AO_TIMESTAMP_CNTL);
val &= 0xFFFFFE00;
- mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val);
+ mmio_write_32(AML_AO_TIMESTAMP_CNTL, val);
- return GXBB_OSC24M_CLK_IN_HZ;
+ return AML_OSC24M_CLK_IN_HZ;
}
/*******************************************************************************
* System oscillator
******************************************************************************/
-#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
+#define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
/*******************************************************************************
* Memory regions
******************************************************************************/
-#define GXBB_NSDRAM0_BASE UL(0x01000000)
-#define GXBB_NSDRAM0_SIZE UL(0x0F000000)
+#define AML_NSDRAM0_BASE UL(0x01000000)
+#define AML_NSDRAM0_SIZE UL(0x0F000000)
-#define GXBB_NSDRAM1_BASE UL(0x10000000)
-#define GXBB_NSDRAM1_SIZE UL(0x00100000)
+#define AML_NSDRAM1_BASE UL(0x10000000)
+#define AML_NSDRAM1_SIZE UL(0x00100000)
#define BL31_BASE UL(0x10100000)
#define BL31_SIZE UL(0x000C0000)
#define AML_SHARE_MEM_INPUT_BASE UL(0x100FE000)
#define AML_SHARE_MEM_OUTPUT_BASE UL(0x100FF000)
-#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000)
-#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000)
+#define AML_SEC_DEVICE0_BASE UL(0xC0000000)
+#define AML_SEC_DEVICE0_SIZE UL(0x09000000)
-#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000)
-#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000)
+#define AML_SEC_DEVICE1_BASE UL(0xD0040000)
+#define AML_SEC_DEVICE1_SIZE UL(0x00008000)
-#define GXBB_TZRAM_BASE UL(0xD9000000)
-#define GXBB_TZRAM_SIZE UL(0x00014000)
+#define AML_TZRAM_BASE UL(0xD9000000)
+#define AML_TZRAM_SIZE UL(0x00014000)
/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
/* Mailboxes */
#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
#define AML_PSCI_MAILBOX_BASE UL(0xD9013F00)
-#define GXBB_TZROM_BASE UL(0xD9040000)
-#define GXBB_TZROM_SIZE UL(0x00010000)
+#define AML_TZROM_BASE UL(0xD9040000)
+#define AML_TZROM_SIZE UL(0x00010000)
-#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000)
-#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000)
+#define AML_SEC_DEVICE2_BASE UL(0xDA000000)
+#define AML_SEC_DEVICE2_SIZE UL(0x00200000)
-#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000)
-#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000)
+#define AML_SEC_DEVICE3_BASE UL(0xDA800000)
+#define AML_SEC_DEVICE3_SIZE UL(0x00200000)
/*******************************************************************************
* GIC-400 and interrupt handling related constants
* UART definitions
******************************************************************************/
#define AML_UART0_AO_BASE UL(0xC81004C0)
-#define AML_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ
+#define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ
#define AML_UART_BAUDRATE U(115200)
/*******************************************************************************
* Memory-mapped I/O Registers
******************************************************************************/
-#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4)
+#define AML_AO_TIMESTAMP_CNTL UL(0xC81000B4)
-#define GXBB_SYS_CPU_CFG7 UL(0xC8834664)
+#define AML_SYS_CPU_CFG7 UL(0xC8834664)
#define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C)
#define PLATFORM_LINKER_ARCH aarch64
/* Special value used to verify platform parameters from BL2 to BL31 */
-#define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
+#define AML_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
#define PLATFORM_STACK_SIZE UL(0x1000)
static inline bool gxl_scp_ready(void)
{
- return GXBB_AO_RTI_SCP_IS_READY(mmio_read_32(GXBB_AO_RTI_SCP_STAT));
+ return AML_AO_RTI_SCP_IS_READY(mmio_read_32(AML_AO_RTI_SCP_STAT));
}
static inline void gxl_scp_boot(void)
/*******************************************************************************
* GICv2 driver setup information
******************************************************************************/
-static const interrupt_prop_t gxbb_interrupt_props[] = {
+static const interrupt_prop_t gxl_interrupt_props[] = {
INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
};
-static const gicv2_driver_data_t gxbb_gic_data = {
+static const gicv2_driver_data_t gxl_gic_data = {
.gicd_base = AML_GICD_BASE,
.gicc_base = AML_GICC_BASE,
- .interrupt_props = gxbb_interrupt_props,
- .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props),
+ .interrupt_props = gxl_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(gxl_interrupt_props),
};
void bl31_platform_setup(void)
{
aml_mhu_secure_init();
- gicv2_driver_init(&gxbb_gic_data);
+ gicv2_driver_init(&gxl_gic_data);
gicv2_distif_init();
gicv2_pcpu_distif_init();
gicv2_cpuif_enable();
/*******************************************************************************
* Platform memory map regions
******************************************************************************/
-#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \
- GXBB_NSDRAM0_SIZE, \
+#define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
+ AML_NSDRAM0_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
-#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \
- GXBB_NSDRAM1_SIZE, \
+#define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
+ AML_NSDRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
-#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \
- GXBB_SEC_DEVICE0_SIZE, \
+#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
+ AML_SEC_DEVICE0_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \
- GXBB_SEC_DEVICE1_SIZE, \
+#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
+ AML_SEC_DEVICE1_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \
- GXBB_TZRAM_SIZE, \
+#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
+ AML_TZRAM_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \
- GXBB_SEC_DEVICE2_SIZE, \
+#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
+ AML_SEC_DEVICE2_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \
- GXBB_SEC_DEVICE3_SIZE, \
+#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
+ AML_SEC_DEVICE3_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-static const mmap_region_t gxbb_mmap[] = {
+static const mmap_region_t gxl_mmap[] = {
MAP_NSDRAM0,
MAP_NSDRAM1,
MAP_SEC_DEVICE0,
void aml_setup_page_tables(void)
{
#if IMAGE_BL31
- const mmap_region_t gxbb_bl_mmap[] = {
+ const mmap_region_t gxl_bl_mmap[] = {
MAP_BL31,
MAP_BL_CODE,
MAP_BL_RO_DATA,
};
#endif
- mmap_add(gxbb_bl_mmap);
+ mmap_add(gxl_bl_mmap);
- mmap_add(gxbb_mmap);
+ mmap_add(gxl_mmap);
init_xlat_tables();
}
/*******************************************************************************
* Function that sets up the console
******************************************************************************/
-static console_meson_t gxbb_console;
+static console_meson_t gxl_console;
void aml_console_init(void)
{
int rc = console_meson_register(AML_UART0_AO_BASE,
AML_UART0_AO_CLK_IN_HZ,
AML_UART_BAUDRATE,
- &gxbb_console);
+ &gxl_console);
if (rc == 0) {
/*
* The crash console doesn't use the multi console API, it uses
panic();
}
- console_set_scope(&gxbb_console.console,
+ console_set_scope(&gxl_console.console,
CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
}
{
uint32_t val;
- val = mmio_read_32(GXBB_SYS_CPU_CFG7);
+ val = mmio_read_32(AML_SYS_CPU_CFG7);
val &= 0xFDFFFFFF;
- mmio_write_32(GXBB_SYS_CPU_CFG7, val);
+ mmio_write_32(AML_SYS_CPU_CFG7, val);
- val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL);
+ val = mmio_read_32(AML_AO_TIMESTAMP_CNTL);
val &= 0xFFFFFE00;
- mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val);
+ mmio_write_32(AML_AO_TIMESTAMP_CNTL, val);
- return GXBB_OSC24M_CLK_IN_HZ;
+ return AML_OSC24M_CLK_IN_HZ;
}
/*******************************************************************************
* System oscillator
******************************************************************************/
-#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
+#define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
/*******************************************************************************
* Memory regions
******************************************************************************/
-#define GXBB_NSDRAM0_BASE UL(0x01000000)
-#define GXBB_NSDRAM0_SIZE UL(0x0F000000)
+#define AML_NSDRAM0_BASE UL(0x01000000)
+#define AML_NSDRAM0_SIZE UL(0x0F000000)
-#define GXBB_NSDRAM1_BASE UL(0x10000000)
-#define GXBB_NSDRAM1_SIZE UL(0x00100000)
+#define AML_NSDRAM1_BASE UL(0x10000000)
+#define AML_NSDRAM1_SIZE UL(0x00100000)
#define BL31_BASE UL(0x05100000)
#define BL31_SIZE UL(0x000C0000)
#define AML_SHARE_MEM_INPUT_BASE UL(0x050FE000)
#define AML_SHARE_MEM_OUTPUT_BASE UL(0x050FF000)
-#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000)
-#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000)
+#define AML_SEC_DEVICE0_BASE UL(0xC0000000)
+#define AML_SEC_DEVICE0_SIZE UL(0x09000000)
-#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000)
-#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000)
+#define AML_SEC_DEVICE1_BASE UL(0xD0040000)
+#define AML_SEC_DEVICE1_SIZE UL(0x00008000)
-#define GXBB_TZRAM_BASE UL(0xD9000000)
-#define GXBB_TZRAM_SIZE UL(0x00014000)
+#define AML_TZRAM_BASE UL(0xD9000000)
+#define AML_TZRAM_SIZE UL(0x00014000)
/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
/* Mailboxes */
// * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) *
// * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) *
-#define GXBB_TZROM_BASE UL(0xD9040000)
-#define GXBB_TZROM_SIZE UL(0x00010000)
+#define AML_TZROM_BASE UL(0xD9040000)
+#define AML_TZROM_SIZE UL(0x00010000)
-#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000)
-#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000)
+#define AML_SEC_DEVICE2_BASE UL(0xDA000000)
+#define AML_SEC_DEVICE2_SIZE UL(0x00200000)
-#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000)
-#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000)
+#define AML_SEC_DEVICE3_BASE UL(0xDA800000)
+#define AML_SEC_DEVICE3_SIZE UL(0x00200000)
/*******************************************************************************
* GIC-400 and interrupt handling related constants
* UART definitions
******************************************************************************/
#define AML_UART0_AO_BASE UL(0xC81004C0)
-#define AML_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ
+#define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ
#define AML_UART_BAUDRATE U(115200)
/*******************************************************************************
* Memory-mapped I/O Registers
******************************************************************************/
-#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4)
+#define AML_AO_TIMESTAMP_CNTL UL(0xC81000B4)
-#define GXBB_SYS_CPU_CFG7 UL(0xC8834664)
+#define AML_SYS_CPU_CFG7 UL(0xC8834664)
#define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C)
-#define GXBB_AO_RTI_SCP_STAT UL(0xDA10023C)
-#define GXBB_AO_RTI_SCP_READY_OFF U(0x14)
-#define GXBB_A0_RTI_SCP_READY_MASK U(3)
-#define GXBB_AO_RTI_SCP_IS_READY(v) \
- ((((v) >> GXBB_AO_RTI_SCP_READY_OFF) & \
- GXBB_A0_RTI_SCP_READY_MASK) == GXBB_A0_RTI_SCP_READY_MASK)
+#define AML_AO_RTI_SCP_STAT UL(0xDA10023C)
+#define AML_AO_RTI_SCP_READY_OFF U(0x14)
+#define AML_A0_RTI_SCP_READY_MASK U(3)
+#define AML_AO_RTI_SCP_IS_READY(v) \
+ ((((v) >> AML_AO_RTI_SCP_READY_OFF) & \
+ AML_A0_RTI_SCP_READY_MASK) == AML_A0_RTI_SCP_READY_MASK)
#define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404)
#define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
projects / project / bcm63xx / atf.git / commitdiff