void __init prom_init(void)
{
uint32_t model = read_model();
+
parse_model(model);
rtl83xx_set_system_type();
priv->r->pie_rule_add(priv, &r->pr);
} else {
int pkts = priv->r->packet_cntr_read(r->pr.packet_cntr);
+
pr_debug("%s: total packets: %d\n", __func__, pkts);
priv->r->pie_rule_write(priv, r->pr.id, &r->pr);
struct rtl838x_port *p = filp->private_data;
u32 value;
size_t res = rtl838x_common_write(buffer, count, ppos, &value);
+
if (res < 0)
return res;
struct rtl838x_port *p = filp->private_data;
u32 value;
size_t res = rtl838x_common_write(buffer, count, ppos, &value);
+
if (res < 0)
return res;
struct dsa_switch *ds = p->dp->ds;
struct rtl838x_switch_priv *priv = ds->priv;
int value;
+
if (priv->family_id == RTL8380_FAMILY_ID)
value = rtl838x_get_egress_rate(priv, p->dp->index);
else
struct rtl838x_switch_priv *priv = ds->priv;
u32 value;
size_t res = rtl838x_common_write(buffer, count, ppos, &value);
+
if (res < 0)
return res;
/* VLANs without members are set back (implicitly) to CIST by DSA */
if (!info.member_ports) {
u16 mst = info.fid;
+
info.fid = 0;
rtldsa_mst_put_slot(priv, mst);
{
struct rtl838x_switch_priv *priv = ds->priv;
unsigned long features = BR_ISOLATED;
+
pr_debug("%s: %d %lX\n", __func__, port, flags.val);
if (priv->r->enable_learning)
features |= BR_LEARNING;
pr_info("Current Intprio2queue setting: %08x\n", sw_r32(RTL839X_QM_INTPRI2QID_CTRL(0)));
for (int i = 0; i < MAX_PRIOS; i++) {
int q = min_queues[i];
+
sw_w32(i << (q * 3), RTL839X_QM_INTPRI2QID_CTRL(q));
}
}
for (block = 0; block < priv->n_pie_blocks; block++) {
for (j = 0; j < 3; j++) {
int t = (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;
+
pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
idx = rtl838x_pie_verify_template(priv, pr, t, block);
if (idx >= 0)
{
for (int i = 0; i < N_FIXED_FIELDS; i++) {
enum template_field_id ft = fixed_templates[t][i];
+
if (field_type == ft)
return true;
}
static void rtl930x_traffic_enable(int source, int dest)
{
struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
+
rtl_table_read(r, source);
sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0));
rtl_table_write(r, source);
static void rtl930x_traffic_disable(int source, int dest)
{
struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
+
rtl_table_read(r, source);
sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0));
rtl_table_write(r, source);
{
for (int i = 0; i < N_FIXED_FIELDS; i++) {
enum template_field_id ft = fixed_templates[t][i];
+
if (field_type == ft)
return true;
}
static void rtl931x_traffic_enable(int source, int dest)
{
struct table_reg *r = rtl_table_get(RTL9310_TBL_2, 1);
+
rtl_table_read(r, source);
sw_w32_mask(0, BIT((dest + 7) % 32), rtl_table_data(r, (dest + 7) / 32 ? 0 : 1));
rtl_table_write(r, source);
static void rtl931x_traffic_disable(int source, int dest)
{
struct table_reg *r = rtl_table_get(RTL9310_TBL_2, 1);
+
rtl_table_read(r, source);
sw_w32_mask(BIT((dest + 7) % 32), 0, rtl_table_data(r, (dest + 7) / 32 ? 0 : 1));
rtl_table_write(r, source);
{
u32 r[4];
struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 1);
+
rtl_table_read(q, idx);
for ( int i = 0; i < 4; i++)
r[i] = sw_r32(rtl_table_data(q, i));
{
u32 r[4];
struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 1);
+
rtl931x_fill_l2_row(r, e);
for (int i = 0; i < 4; i++)
{
for (int i = 0; i < N_FIXED_FIELDS_RTL931X; i++) {
enum template_field_id ft = fixed_templates[t][i];
+
if (field_type == ft)
return true;
}
for (block = min_block; block < max_block; block++) {
for (j = 0; j < 2; j++) {
int t = (sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;
+
pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
pr_debug("%s: %08x\n",
__func__, sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)));
if (priv->family_id == RTL8380_FAMILY_ID) {
for (int i = 0; i < 10; i++) {
u32 val = sw_r32(priv->r->dma_if_ctrl);
+
if ((val & 0xc) == 0xc)
break;
}
while (work_done < budget) {
int work = rtl838x_hw_receive(priv->netdev, ring, budget - work_done);
+
if (!work)
break;
work_done += work;
static int rtpcs_931x_sds_link_sts_get(struct rtpcs_ctrl *ctrl, u32 sds)
{
u32 sts, sts1, latch_sts, latch_sts1;
+
if (0){
sts = rtpcs_sds_read_bits(ctrl, sds, 0x41, 29, 8, 0);
sts1 = rtpcs_sds_read_bits(ctrl, sds, 0x81, 29, 8, 0);