bl31: Add error reporting registers

This patch adds cpumerrsr_el1 and l2merrsr_el1 to the register dump on
error for applicable CPUs.

These registers hold the ECC errors on L1 and L2 caches.

This patch updates the A53, A57, A72, A73 (l2merrsr_el1 only) CPU libraries.

Signed-off-by: Naga Sureshkumar Relli <[email protected]>

diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 169d8f4b6985d6714ac1f3911e6df5d860d38011..6976b809aad5a73404737aa12b65bfe56abccc0d 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -56,6 +56,11 @@
 #define CPUECTLR_FPU_RET_CTRL_SHIFT    3
 #define CPUECTLR_FPU_RET_CTRL_MASK     (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT)
 
+/*******************************************************************************
+ * CPU Memory Error Syndrome register specific definitions.
+ ******************************************************************************/
+#define CPUMERRSR_EL1                  S3_1_C15_C2_2   /* Instruction def. */
+
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
@@ -79,4 +84,9 @@
 #define L2ECTLR_RET_CTRL_SHIFT         0
 #define L2ECTLR_RET_CTRL_MASK          (0x7 << L2ECTLR_RET_CTRL_SHIFT)
 
+/*******************************************************************************
+ * L2 Memory Error Syndrome register specific definitions.
+ ******************************************************************************/
+#define L2MERRSR_EL1                   S3_1_C15_C2_3   /* Instruction def. */
+
 #endif /* __CORTEX_A53_H__ */

diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index ac4ae57017bea84a33860256f513344b0f148367..c5a218b72549eba39116500972c2a86cc3a4ed13 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -56,6 +56,11 @@
 #define CPUECTLR_CPU_RET_CTRL_SHIFT    0
 #define CPUECTLR_CPU_RET_CTRL_MASK     (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
 
+/*******************************************************************************
+ * CPU Memory Error Syndrome register specific definitions.
+ ******************************************************************************/
+#define CPUMERRSR_EL1                  S3_1_C15_C2_2   /* Instruction def. */
+
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
@@ -90,4 +95,9 @@
 #define L2ECTLR_RET_CTRL_SHIFT         0
 #define L2ECTLR_RET_CTRL_MASK          (0x7 << L2ECTLR_RET_CTRL_SHIFT)
 
+/*******************************************************************************
+ * L2 Memory Error Syndrome register specific definitions.
+ ******************************************************************************/
+#define L2MERRSR_EL1                   S3_1_C15_C2_3   /* Instruction def. */
+
 #endif /* __CORTEX_A57_H__ */

diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index fa10ca90254660317a190e5e24c257863d008da2..01edf43b9105748f2ba615bb77353ae75aec752a 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -44,6 +44,11 @@
 #define CPUECTLR_L2_IPFTCH_DIST_MASK   (0x3 << 35)
 #define CPUECTLR_L2_DPFTCH_DIST_MASK   (0x3 << 32)
 
+/*******************************************************************************
+ * CPU Memory Error Syndrome register specific definitions.
+ ******************************************************************************/
+#define CPUMERRSR_EL1                  S3_1_C15_C2_2   /* Instruction def. */
+
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
@@ -65,4 +70,9 @@
 #define L2_TAG_RAM_LATENCY_2_CYCLES    0x1
 #define L2_TAG_RAM_LATENCY_3_CYCLES    0x2
 
+/*******************************************************************************
+ * L2 Memory Error Syndrome register specific definitions.
+ ******************************************************************************/
+#define L2MERRSR_EL1                   S3_1_C15_C2_3   /* Instruction def. */
+
 #endif /* __CORTEX_A72_H__ */

diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h
index 2ad04677d9ecedc14e723ca4cafc9ad2d031850b..13e114a3cea494ecfa30dc991918dbf5a6c1c25b 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a73.h
+++ b/include/lib/cpus/aarch64/cortex_a73.h
@@ -41,4 +41,9 @@
 
 #define CORTEX_A73_CPUECTLR_SMP_BIT    (1 << 6)
 
+/*******************************************************************************
+ * L2 Memory Error Syndrome register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A73_L2MERRSR_EL1                S3_1_C15_C2_3   /* Instruction def. */
+
 #endif /* __CORTEX_A73_H__ */

diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index bb565162962f2f9adaef54960cd6062e8fbb53dc..ed546e7eaf20acab14b285508f5e8c84703581ed 100644 (file)
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -234,11 +234,13 @@ endfunc cortex_a53_cluster_pwr_dwn
         */
 .section .rodata.cortex_a53_regs, "aS"
 cortex_a53_regs:  /* The ascii list of register names to be reported */
-       .asciz  "cpuectlr_el1", ""
+       .asciz  "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", ""
 
 func cortex_a53_cpu_reg_dump
        adr     x6, cortex_a53_regs
        mrs     x8, CPUECTLR_EL1
+       mrs     x9, CPUMERRSR_EL1
+       mrs     x10, L2MERRSR_EL1
        ret
 endfunc cortex_a53_cpu_reg_dump
 

diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 60929a0506f22eab26b41a4b5f52f060294c7577..d6b181d02f622dabc03d4ab4782521929b8bd5a6 100644 (file)
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -477,11 +477,13 @@ endfunc cortex_a57_cluster_pwr_dwn
         */
 .section .rodata.cortex_a57_regs, "aS"
 cortex_a57_regs:  /* The ascii list of register names to be reported */
-       .asciz  "cpuectlr_el1", ""
+       .asciz  "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", ""
 
 func cortex_a57_cpu_reg_dump
        adr     x6, cortex_a57_regs
        mrs     x8, CPUECTLR_EL1
+       mrs     x9, CPUMERRSR_EL1
+       mrs     x10, L2MERRSR_EL1
        ret
 endfunc cortex_a57_cpu_reg_dump
 

diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S
index eb37f2ca9a6b09f4c76078187c3ea0e0a698e481..9f04fb72ae007fd6d237613289a10d589b4303a6 100644 (file)
--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S
@@ -231,11 +231,13 @@ endfunc cortex_a72_cluster_pwr_dwn
         */
 .section .rodata.cortex_a72_regs, "aS"
 cortex_a72_regs:  /* The ascii list of register names to be reported */
-       .asciz  "cpuectlr_el1", ""
+       .asciz  "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", ""
 
 func cortex_a72_cpu_reg_dump
        adr     x6, cortex_a72_regs
        mrs     x8, CPUECTLR_EL1
+       mrs     x9, CPUMERRSR_EL1
+       mrs     x10, L2MERRSR_EL1
        ret
 endfunc cortex_a72_cpu_reg_dump
 

diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S
index 70b4c6a570e94059f5bbac3c857309f078fe4b36..e1615dbd7482344a97166919ae22a805d8a769c7 100644 (file)
--- a/lib/cpus/aarch64/cortex_a73.S
+++ b/lib/cpus/aarch64/cortex_a73.S
@@ -144,11 +144,12 @@ endfunc cortex_a73_cluster_pwr_dwn
         */
 .section .rodata.cortex_a73_regs, "aS"
 cortex_a73_regs:  /* The ascii list of register names to be reported */
-       .asciz  "cpuectlr_el1", ""
+       .asciz  "cpuectlr_el1", "l2merrsr_el1", ""
 
 func cortex_a73_cpu_reg_dump
        adr     x6, cortex_a73_regs
        mrs     x8, CORTEX_A73_CPUECTLR_EL1
+       mrs     x9, CORTEX_A73_L2MERRSR_EL1
        ret
 endfunc cortex_a73_cpu_reg_dump