drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix

This is a WA affecting pooled eu which is a bxt specific feature.

Reviewed-by: Mika Kuoppala <[email protected]>
Cc: Winiarski, Michal <[email protected]>
Cc: Zou, Nanhai <[email protected]>
Cc: Yang, Rong R <[email protected]>
Cc: Jeff McGee <[email protected]>
Signed-off-by: Arun Siluvery <[email protected]>
Signed-off-by: Tvrtko Ursulin <[email protected]>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4058d6f66f5aaacfe26d463daf901c75cfe1196f..8a729c95e80eed736d258bcf3b2ce70bd4c66c74 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6106,6 +6106,7 @@ enum skl_disp_power_wells {
 
 #define FF_SLICE_CS_CHICKEN2                   _MMIO(0x20e4)
 #define  GEN9_TSG_BARRIER_ACK_DISABLE          (1<<8)
+#define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1<<10)
 
 #define GEN9_CS_DEBUG_MODE1            _MMIO(0x20ec)
 #define GEN9_CTX_PREEMPT_REG           _MMIO(0x2248)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 110c7fc957b7858e00bd277c37518ad2820d2810..fedd270498140945d6b4167c8b2844833b46e2a1 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1160,6 +1160,12 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
        WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
                          STALL_DOP_GATING_DISABLE);
 
+       /* WaDisablePooledEuLoadBalancingFix:bxt */
+       if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
+               WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
+                                 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
+       }
+
        /* WaDisableSbeCacheDispatchPortSharing:bxt */
        if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
                WA_SET_BIT_MASKED(