plat: imx8mq: Only keep IRQ 32 unmasked

Only IRQ 32 (SPI 0) needs to be kept unmasked, not everything divisible
by 32.

Signed-off-by: Leonard Crestez <[email protected]>
Change-Id: I286b925eead89218cfeddd82f53a634f3447d212

diff --git a/plat/imx/imx8m/imx8mq/gpc.c b/plat/imx/imx8m/imx8mq/gpc.c
index 107b53913669dc6ff410fd4b4798dd80ac3dafd4..942ae459cffabd2465818a013c3c5df23de02483 100644 (file)
--- a/plat/imx/imx8m/imx8mq/gpc.c
+++ b/plat/imx/imx8m/imx8mq/gpc.c
@@ -119,17 +119,21 @@ void imx_gpc_init(void)
        uint32_t val;
        int i;
        /* mask all the interrupt by default */
+       for (i = 0; i < 4; i++) {
+               mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);
+               mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);
+               mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);
+               mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);
+               mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
+       }
        /* Due to the hardware design requirement, need to make
         * sure GPR interrupt(#32) is unmasked during RUN mode to
         * avoid entering DSM mode by mistake.
         */
-       for (i = 0; i < 4; i++) {
-               mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, 0xFFFFFFFE);
-               mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, 0xFFFFFFFE);
-               mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, 0xFFFFFFFE);
-               mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, 0xFFFFFFFE);
-               mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
-       }
+       mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53, 0xFFFFFFFE);
+       mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53, 0xFFFFFFFE);
+       mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53, 0xFFFFFFFE);
+       mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53, 0xFFFFFFFE);
 
        /* use external IRQs to wakeup C0~C3 from LPM */
        val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);