x86/RAS: Add SMCA support to AMD Error Injector

Use SMCA MSRs when writing to MCA_{STATUS,ADDR,MISC} and
MCA_DE{STAT,ADDR} when injecting Deferred Errors on SMCA platforms.

Signed-off-by: Yazen Ghannam <[email protected]>
Signed-off-by: Borislav Petkov <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: Aravind Gopalakrishnan <[email protected]>
Cc: Borislav Petkov <[email protected]>
Cc: Brian Gerst <[email protected]>
Cc: Denys Vlasenko <[email protected]>
Cc: H. Peter Anvin <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Tony Luck <[email protected]>
Cc: linux-edac <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>

diff --git a/arch/x86/ras/mce_amd_inj.c b/arch/x86/ras/mce_amd_inj.c
index 9e02dcaef68311ed376f8fcd0579d6c207e80103..e69f4701a076da1006c85532de3a585822c2578f 100644 (file)
--- a/arch/x86/ras/mce_amd_inj.c
+++ b/arch/x86/ras/mce_amd_inj.c
@@ -290,14 +290,33 @@ static void do_inject(void)
        wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS,
                     (u32)mcg_status, (u32)(mcg_status >> 32));
 
-       wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),
-                    (u32)i_mce.status, (u32)(i_mce.status >> 32));
+       if (boot_cpu_has(X86_FEATURE_SMCA)) {
+               if (inj_type == DFR_INT_INJ) {
+                       wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_DESTAT(b),
+                                    (u32)i_mce.status, (u32)(i_mce.status >> 32));
+
+                       wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_DEADDR(b),
+                                    (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
+               } else {
+                       wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_STATUS(b),
+                                    (u32)i_mce.status, (u32)(i_mce.status >> 32));
+
+                       wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_ADDR(b),
+                                    (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
+               }
+
+               wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(b),
+                            (u32)i_mce.misc, (u32)(i_mce.misc >> 32));
+       } else {
+               wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),
+                            (u32)i_mce.status, (u32)(i_mce.status >> 32));
 
-       wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b),
-                    (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
+               wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b),
+                            (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
 
-       wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),
-                    (u32)i_mce.misc, (u32)(i_mce.misc >> 32));
+               wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),
+                            (u32)i_mce.misc, (u32)(i_mce.misc >> 32));
+       }
 
        toggle_hw_mce_inject(cpu, false);