};
&pcie_bridge0 {
- wifi2: wifi@0,0 {
+ wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
- status = "okay";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&cal_factory_9000>;
nvmem-cell-names = "calibration";
};
&pcie_bridge0 {
- wifi@0,0 {
+ wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-sa-gpio = <2 3 4 0>;
};
&pcie_bridge1 {
- wifi@0,0 {
+ wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-sa-gpio = <2 3 4 0>;
};
&pcie_bridge2 {
- wifi@0,0 {
+ wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
};
&pci1 {
status = "okay";
- wifi@0,0 {
+ wifi@1,0 {
compatible = "pci1814,3091";
reg = <0x10000 0 0 0 0>;
nvmem-cells = <&eeprom_factory_8000>;
&pci1 {
status = "okay";
- wifi@0,0 {
+ wifi@1,0 {
compatible = "pci0,0";
reg = <0x10000 0 0 0 0>;
ralink,5ghz = <0>;
&pci1 {
status = "okay";
- wifi@0,0 {
+ wifi@1,0 {
compatible = "pci1814,3091";
reg = <0x10000 0 0 0 0>;
ralink,5ghz = <0>;
&pci1 {
status = "okay";
- wifi@0,0 {
+ wifi@1,0 {
compatible = "pci1814,3091";
reg = <0x10000 0 0 0 0>;
nvmem-cells = <&eeprom_factory_2000>;
&pci1 {
status = "okay";
- wifi@0,0 {
+ wifi@1,0 {
compatible = "pci1814,3091";
reg = <0x10000 0 0 0 0>;
nvmem-cells = <&eeprom_factory_8000>;
&pci1 {
status = "okay";
- wifi@0,0 {
+ wifi@1,0 {
compatible = "pci1814,3091";
reg = <0x10000 0 0 0 0>;
nvmem-cells = <&eeprom_factory_8000>;
&pci1 {
status = "okay";
- wifi@0,0 {
+ wifi@1,0 {
compatible = "pci0,0";
reg = < 0x10000 0 0 0 0 >;
ralink,2ghz = <0>;