omap3: clock: Fixed dpll3_m2x2 rate calculation

Current calculation does not take into account any changes to M2 divisor, and
thus when we change VDD2 OPP, dpll3_m2x2 rate does not change. Fixed by
re-routing dpll3_m2x2 parent to dpll3_m2.

Signed-off-by: Tero Kristo <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index c8119781e00aff7f0be0e7965dbd14878edcb55a..9565c05bebd259d050afc597e7578294403470c7 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -489,9 +489,9 @@ static struct clk core_ck = {
 static struct clk dpll3_m2x2_ck = {
        .name           = "dpll3_m2x2_ck",
        .ops            = &clkops_null,
-       .parent         = &dpll3_x2_ck,
+       .parent         = &dpll3_m2_ck,
        .clkdm_name     = "dpll3_clkdm",
-       .recalc         = &followparent_recalc,
+       .recalc         = &omap3_clkoutx2_recalc,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */