realtek: fix PLL register inconsistencies

Some devices have wrong/empty values in the PLL registers. Work
around that by reporting the default values.

Signed-off-by: Markus Stockhausen <[email protected]>

diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
index c3eb270f6e935d999b3ff34e9d6ba253a06b8816..9b8183fbebd6bc3540933ff9b5ae28b836577d76 100644 (file)
--- a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
+++ b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
@@ -366,6 +366,9 @@ static unsigned long rtcl_recalc_rate(struct clk_hw *hw, unsigned long parent_ra
 
        switch (rtcl_ccu->soc) {
        case SOC_RTL838X:
+               if ((ctrl0 == 0) && (ctrl1 == 0) && (clk->idx == CLK_LXB))
+                       return 200000000;
+
                cmu_divn2_selb = RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(ctrl1);
                cmu_divn3_sel = rtcl_divn3[RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(ctrl1)];
                break;