#ifdef CONFIG_RTL839X
/* disable MIPS 34K branch and return prediction */
- mfc0 rCP0, CP0_CONFIG, 7
- ori rTMP, rCP0, 0xc
- mtc0 rTMP, CP0_CONFIG, 7
+ mfc0 rCP0, CP0_CONFIG, 7
+ ori rTMP, rCP0, 0xc
+ mtc0 rTMP, CP0_CONFIG, 7
li rCTR, RTL_SW_CORE_BASE
addiu rGLB, rCTR, RTL839X_PLL_GLB_CTRL
*/
#define RTCL_SRAM_FUNC(SOC, PBASE, FN) ({ \
- rtcl_##SOC##_sram_##FN = ((void *)&rtcl_##SOC##_dram_##FN - \
- (void *)&rtcl_##SOC##_dram_start) + \
- (void *)PBASE; })
+ rtcl_##SOC##_sram_##FN = ((void *)&rtcl_##SOC##_dram_##FN - \
+ (void *)&rtcl_##SOC##_dram_start) + \
+ (void *)PBASE; })
static const struct clk_ops rtcl_clk_ops = {
.set_rate = rtcl_set_rate,
dev_info(priv->dev, "%s IPv4 route %pI4/%d %s(VLAN %d, MAC %pM)\n",
event == FIB_EVENT_ENTRY_ADD ? "add" : "delete",
&info->dst, info->dst_len, gw_message, vlan, ndev->dev_addr);
-
+
if ((info->type == RTN_BROADCAST) || ipv4_is_loopback(info->dst) || !info->dst) {
dev_warn(priv->dev, "skip loopback/broadcast addresses and default routes\n");
return -EINVAL;
m.p_id = 0x3f; /* Listen on any port */
m.p_id_mask = 0;
m.vid = 0; /* Listen on any VLAN... */
- m.vid_mask = 0; /* ... so mask needs to be 0 */
+ m.vid_mask = 0; /* ... so mask needs to be 0 */
m.mac_mask = 0xffffffffffffULL; /* We want an exact match of the interface MAC */
m.action = L3_FORWARD; /* Route the packet */
priv->r->set_l3_router_mac(free_mac, &m);
of_node_put(ports);
- return ret;
+ return ret;
}
static int __init rtl83xx_sw_probe(struct platform_device *pdev)
dev_err(dev, "No DT found\n");
return -EINVAL;
}
-
+
err = rtldsa_ethernet_loaded(pdev);
if (err)
return err;
switch (priv->family_id) {
case RTL8380_FAMILY_ID:
err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
- IRQF_SHARED, "rtl838x-link-state", priv->ds);
+ IRQF_SHARED, "rtl838x-link-state", priv->ds);
break;
case RTL8390_FAMILY_ID:
err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
- IRQF_SHARED, "rtl839x-link-state", priv->ds);
+ IRQF_SHARED, "rtl839x-link-state", priv->ds);
break;
case RTL9300_FAMILY_ID:
err = request_irq(priv->link_state_irq, rtldsa_930x_switch_irq,
break;
case RTL9310_FAMILY_ID:
err = request_irq(priv->link_state_irq, rtl931x_switch_irq,
- IRQF_SHARED, "rtl931x-link-state", priv->ds);
+ IRQF_SHARED, "rtl931x-link-state", priv->ds);
break;
}
if (err) {
#define RTL931X_STAT_PRVTE_DROP_COUNTERS (0xd800)
const char *rtl838x_drop_cntr[] = {
- "ALE_TX_GOOD_PKTS", "MAC_RX_DROP", "ACL_FWD_DROP", "HW_ATTACK_PREVENTION_DROP",
- "RMA_DROP", "VLAN_IGR_FLTR_DROP", "INNER_OUTER_CFI_EQUAL_1_DROP", "PORT_MOVE_DROP",
- "NEW_SA_DROP", "MAC_LIMIT_SYS_DROP", "MAC_LIMIT_VLAN_DROP", "MAC_LIMIT_PORT_DROP",
- "SWITCH_MAC_DROP", "ROUTING_EXCEPTION_DROP", "DA_LKMISS_DROP", "RSPAN_DROP",
- "ACL_LKMISS_DROP", "ACL_DROP", "INBW_DROP", "IGR_METER_DROP",
- "ACCEPT_FRAME_TYPE_DROP", "STP_IGR_DROP", "INVALID_SA_DROP", "SA_BLOCKING_DROP",
- "DA_BLOCKING_DROP", "L2_INVALID_DPM_DROP", "MCST_INVALID_DPM_DROP", "RX_FLOW_CONTROL_DROP",
- "STORM_SPPRS_DROP", "LALS_DROP", "VLAN_EGR_FILTER_DROP", "STP_EGR_DROP",
- "SRC_PORT_FILTER_DROP", "PORT_ISOLATION_DROP", "ACL_FLTR_DROP", "MIRROR_FLTR_DROP",
- "TX_MAX_DROP", "LINK_DOWN_DROP", "FLOW_CONTROL_DROP", "BRIDGE .1d discards"
+ "ALE_TX_GOOD_PKTS", "MAC_RX_DROP", "ACL_FWD_DROP", "HW_ATTACK_PREVENTION_DROP",
+ "RMA_DROP", "VLAN_IGR_FLTR_DROP", "INNER_OUTER_CFI_EQUAL_1_DROP", "PORT_MOVE_DROP",
+ "NEW_SA_DROP", "MAC_LIMIT_SYS_DROP", "MAC_LIMIT_VLAN_DROP", "MAC_LIMIT_PORT_DROP",
+ "SWITCH_MAC_DROP", "ROUTING_EXCEPTION_DROP", "DA_LKMISS_DROP", "RSPAN_DROP",
+ "ACL_LKMISS_DROP", "ACL_DROP", "INBW_DROP", "IGR_METER_DROP",
+ "ACCEPT_FRAME_TYPE_DROP", "STP_IGR_DROP", "INVALID_SA_DROP", "SA_BLOCKING_DROP",
+ "DA_BLOCKING_DROP", "L2_INVALID_DPM_DROP", "MCST_INVALID_DPM_DROP", "RX_FLOW_CONTROL_DROP",
+ "STORM_SPPRS_DROP", "LALS_DROP", "VLAN_EGR_FILTER_DROP", "STP_EGR_DROP",
+ "SRC_PORT_FILTER_DROP", "PORT_ISOLATION_DROP", "ACL_FLTR_DROP", "MIRROR_FLTR_DROP",
+ "TX_MAX_DROP", "LINK_DOWN_DROP", "FLOW_CONTROL_DROP", "BRIDGE .1d discards"
};
const char *rtl839x_drop_cntr[] = {
- "ALE_TX_GOOD_PKTS", "ERROR_PKTS", "EGR_ACL_DROP", "EGR_METER_DROP",
- "OAM", "CFM" "VLAN_IGR_FLTR", "VLAN_ERR",
- "INNER_OUTER_CFI_EQUAL_1", "VLAN_TAG_FORMAT", "SRC_PORT_SPENDING_TREE", "INBW",
- "RMA", "HW_ATTACK_PREVENTION", "PROTO_STORM", "MCAST_SA",
- "IGR_ACL_DROP", "IGR_METER_DROP", "DFLT_ACTION_FOR_MISS_ACL_AND_C2SC", "NEW_SA",
- "PORT_MOVE", "SA_BLOCKING", "ROUTING_EXCEPTION", "SRC_PORT_SPENDING_TREE_NON_FWDING",
- "MAC_LIMIT", "UNKNOW_STORM", "MISS_DROP", "CPU_MAC_DROP",
- "DA_BLOCKING", "SRC_PORT_FILTER_BEFORE_EGR_ACL", "VLAN_EGR_FILTER", "SPANNING_TRE",
- "PORT_ISOLATION", "OAM_EGRESS_DROP", "MIRROR_ISOLATION", "MAX_LEN_BEFORE_EGR_ACL",
- "SRC_PORT_FILTER_BEFORE_MIRROR", "MAX_LEN_BEFORE_MIRROR", "SPECIAL_CONGEST_BEFORE_MIRROR",
- "LINK_STATUS_BEFORE_MIRROR",
- "WRED_BEFORE_MIRROR", "MAX_LEN_AFTER_MIRROR", "SPECIAL_CONGEST_AFTER_MIRROR",
- "LINK_STATUS_AFTER_MIRROR",
- "WRED_AFTER_MIRROR"
+ "ALE_TX_GOOD_PKTS", "ERROR_PKTS", "EGR_ACL_DROP", "EGR_METER_DROP",
+ "OAM", "CFM" "VLAN_IGR_FLTR", "VLAN_ERR",
+ "INNER_OUTER_CFI_EQUAL_1", "VLAN_TAG_FORMAT", "SRC_PORT_SPENDING_TREE", "INBW",
+ "RMA", "HW_ATTACK_PREVENTION", "PROTO_STORM", "MCAST_SA",
+ "IGR_ACL_DROP", "IGR_METER_DROP", "DFLT_ACTION_FOR_MISS_ACL_AND_C2SC", "NEW_SA",
+ "PORT_MOVE", "SA_BLOCKING", "ROUTING_EXCEPTION", "SRC_PORT_SPENDING_TREE_NON_FWDING",
+ "MAC_LIMIT", "UNKNOW_STORM", "MISS_DROP", "CPU_MAC_DROP",
+ "DA_BLOCKING", "SRC_PORT_FILTER_BEFORE_EGR_ACL", "VLAN_EGR_FILTER", "SPANNING_TRE",
+ "PORT_ISOLATION", "OAM_EGRESS_DROP", "MIRROR_ISOLATION", "MAX_LEN_BEFORE_EGR_ACL",
+ "SRC_PORT_FILTER_BEFORE_MIRROR", "MAX_LEN_BEFORE_MIRROR", "SPECIAL_CONGEST_BEFORE_MIRROR",
+ "LINK_STATUS_BEFORE_MIRROR",
+ "WRED_BEFORE_MIRROR", "MAX_LEN_AFTER_MIRROR", "SPECIAL_CONGEST_AFTER_MIRROR",
+ "LINK_STATUS_AFTER_MIRROR",
+ "WRED_AFTER_MIRROR"
};
const char *rtl930x_drop_cntr[] = {
mac_stats->OctetsReceivedOK = counters->if_in_octets.val -
18 * mac_stats->FramesReceivedOK;
mac_stats->OctetsTransmittedOK = counters->if_out_octets.val -
- 18 * mac_stats->FramesTransmittedOK;
+ 18 * mac_stats->FramesTransmittedOK;
mac_stats->SingleCollisionFrames = counters->single_collisions.val;
mac_stats->MultipleCollisionFrames = counters->multiple_collisions.val;
* given, true when @mst_slot is now unused
*/
static bool rtldsa_mst_put_slot(struct rtl838x_switch_priv *priv, u16 mst_slot)
- __must_hold(&priv->reg_mutex)
+ __must_hold(&priv->reg_mutex)
{
unsigned int index;
static void rtl839x_read_scheduling_table(int port)
{
u32 cmd = 1 << 9 | /* Execute cmd */
- 0 << 8 | /* Read */
- 0 << 6 | /* Table type 0b00 */
- (port & 0x3f);
+ 0 << 8 | /* Read */
+ 0 << 6 | /* Table type 0b00 */
+ (port & 0x3f);
rtl839x_exec_tbl2_cmd(cmd);
}
static void rtl839x_write_scheduling_table(int port)
{
u32 cmd = 1 << 9 | /* Execute cmd */
- 1 << 8 | /* Write */
- 0 << 6 | /* Table type 0b00 */
- (port & 0x3f);
+ 1 << 8 | /* Write */
+ 0 << 6 | /* Table type 0b00 */
+ (port & 0x3f);
rtl839x_exec_tbl2_cmd(cmd);
}
static void rtl839x_read_out_q_table(int port)
{
u32 cmd = 1 << 9 | /* Execute cmd */
- 0 << 8 | /* Read */
- 2 << 6 | /* Table type 0b10 */
- (port & 0x3f);
+ 0 << 8 | /* Read */
+ 2 << 6 | /* Table type 0b10 */
+ (port & 0x3f);
rtl839x_exec_tbl2_cmd(cmd);
}
static void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
{
u32 cmd = 1 << 15 | /* Execute cmd */
- 1 << 14 | /* Read */
- 2 << 12 | /* Table type 0b10 */
- (msti & 0xfff);
+ 1 << 14 | /* Read */
+ 2 << 12 | /* Table type 0b10 */
+ (msti & 0xfff);
priv->r->exec_tbl0_cmd(cmd);
for (int i = 0; i < 2; i++)
static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
{
u32 cmd = 1 << 15 | /* Execute cmd */
- 0 << 14 | /* Write */
- 2 << 12 | /* Table type 0b10 */
- (msti & 0xfff);
+ 0 << 14 | /* Write */
+ 2 << 12 | /* Table type 0b10 */
+ (msti & 0xfff);
for (int i = 0; i < 2; i++)
sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
#define RTL839X_IGR_BWCTRL_CTRL_LB_THR (0x1614)
/* Link aggregation (Trunking) */
-#define TRUNK_DISTRIBUTION_ALGO_SPA_BIT 0x01
-#define TRUNK_DISTRIBUTION_ALGO_SMAC_BIT 0x02
-#define TRUNK_DISTRIBUTION_ALGO_DMAC_BIT 0x04
-#define TRUNK_DISTRIBUTION_ALGO_SIP_BIT 0x08
-#define TRUNK_DISTRIBUTION_ALGO_DIP_BIT 0x10
-#define TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT 0x20
-#define TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT 0x40
-#define TRUNK_DISTRIBUTION_ALGO_MASKALL 0x7F
-
-#define TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT 0x01
-#define TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT 0x02
-#define TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT 0x04
-#define TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT 0x08
-#define TRUNK_DISTRIBUTION_ALGO_L2_MASKALL 0xF
-
-#define TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT 0x01
-#define TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT 0x02
-#define TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT 0x04
-#define TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT 0x08
-#define TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT 0x10
-#define TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT 0x20
+#define TRUNK_DISTRIBUTION_ALGO_SPA_BIT 0x01
+#define TRUNK_DISTRIBUTION_ALGO_SMAC_BIT 0x02
+#define TRUNK_DISTRIBUTION_ALGO_DMAC_BIT 0x04
+#define TRUNK_DISTRIBUTION_ALGO_SIP_BIT 0x08
+#define TRUNK_DISTRIBUTION_ALGO_DIP_BIT 0x10
+#define TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT 0x20
+#define TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT 0x40
+#define TRUNK_DISTRIBUTION_ALGO_MASKALL 0x7F
+
+#define TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT 0x01
+#define TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT 0x02
+#define TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT 0x04
+#define TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT 0x08
+#define TRUNK_DISTRIBUTION_ALGO_L2_MASKALL 0xF
+
+#define TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT 0x01
+#define TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT 0x02
+#define TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT 0x04
+#define TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT 0x08
+#define TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT 0x10
+#define TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT 0x20
#define TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT 0x40
#define TRUNK_DISTRIBUTION_ALGO_L3_DST_L4PORT_BIT 0x80
-#define TRUNK_DISTRIBUTION_ALGO_L3_PROTO_BIT 0x100
+#define TRUNK_DISTRIBUTION_ALGO_L3_PROTO_BIT 0x100
#define TRUNK_DISTRIBUTION_ALGO_L3_FLOW_LABEL_BIT 0x200
-#define TRUNK_DISTRIBUTION_ALGO_L3_MASKALL 0x3FF
+#define TRUNK_DISTRIBUTION_ALGO_L3_MASKALL 0x3FF
-#define RTL838X_TRK_MBR_CTR (0x3E00)
-#define RTL838X_TRK_HASH_IDX_CTRL (0x3E20)
-#define RTL838X_TRK_HASH_CTRL (0x3E24)
+#define RTL838X_TRK_MBR_CTR (0x3E00)
+#define RTL838X_TRK_HASH_IDX_CTRL (0x3E20)
+#define RTL838X_TRK_HASH_CTRL (0x3E24)
-#define RTL839X_TRK_MBR_CTR (0x2200)
-#define RTL839X_TRK_HASH_IDX_CTRL (0x2280)
-#define RTL839X_TRK_HASH_CTRL (0x2284)
+#define RTL839X_TRK_MBR_CTR (0x2200)
+#define RTL839X_TRK_HASH_IDX_CTRL (0x2280)
+#define RTL839X_TRK_HASH_CTRL (0x2284)
-#define RTL930X_TRK_MBR_CTRL (0xA41C)
-#define RTL930X_TRK_HASH_CTRL (0x9F80)
+#define RTL930X_TRK_MBR_CTRL (0xA41C)
+#define RTL930X_TRK_HASH_CTRL (0x9F80)
-#define RTL931X_TRK_MBR_CTRL (0xB8D0)
-#define RTL931X_TRK_HASH_CTRL (0xBA70)
+#define RTL931X_TRK_MBR_CTRL (0xB8D0)
+#define RTL931X_TRK_HASH_CTRL (0xBA70)
/* Attack prevention */
#define RTL838X_ATK_PRVNT_PORT_EN (0x5B00)
#define RTL838X_QM_PKT2CPU_INTPRI_1 (0x5F08)
#define RTL838X_QM_PKT2CPU_INTPRI_2 (0x5F0C)
#define RTL839X_OAM_CTRL (0x2100)
-#define RTL839X_OAM_PORT_ACT_CTRL(p) (0x2104 + (((p) << 2)))
+#define RTL839X_OAM_PORT_ACT_CTRL(p) (0x2104 + (((p) << 2)))
#define RTL839X_RMK_PORT_DEI_TAG_CTRL(p) (0x6A9C + (((p >> 5) << 2)))
#define RTL839X_PRI_SEL_IPRI_REMAP (0x1080)
#define RTL838X_PRI_SEL_IPRI_REMAP (0x5F8C)
#define RTL839X_PRI_SEL_DSCP2DP_REMAP_ADDR(i) (0x10F0 + (((i >> 4) << 2)))
#define RTL839X_RMK_DEI_CTRL (0x6AA4)
#define RTL839X_WRED_PORT_THR_CTRL(i) (0x6084 + ((i) << 2))
-#define RTL839X_WRED_QUEUE_THR_CTRL(q, i) (0x6090 + ((q) * 12) + ((i) << 2))
+#define RTL839X_WRED_QUEUE_THR_CTRL(q, i) (0x6090 + ((q) * 12) + ((i) << 2))
#define RTL838X_PRI_DSCP_INVLD_CTRL0 (0x5FE8)
#define RTL838X_RMK_IPRI_CTRL (0xA460)
#define RTL838X_RMK_OPRI_CTRL (0xA464)
#define ROUTE_ACT_DROP 3
/* L3 Routing */
-#define RTL839X_ROUTING_SA_CTRL 0x6afc
+#define RTL839X_ROUTING_SA_CTRL 0x6afc
#define RTL930X_L3_HOST_TBL_CTRL (0xAB48)
#define RTL930X_L3_IPUC_ROUTE_CTRL (0xAB4C)
#define RTL930X_L3_IP6UC_ROUTE_CTRL (0xAB50)
u32 h1, h2, h;
if (sw_r32(priv->r->l2_ctrl_0) & 1) {
- h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f) ^
- ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f) ^
- ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
- h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f) ^
- ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f) ^
- (seed & 0x3f));
+ h1 = (u32)(((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f) ^
+ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f) ^
+ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
+ h2 = (u32)(((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f) ^
+ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f) ^
+ (seed & 0x3f));
h = (h1 << 6) | h2;
} else {
h = (seed >> 60) ^
static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
{
u32 cmd = 1 << 16 | /* Execute cmd */
- 0 << 15 | /* Read */
- 5 << 12 | /* Table type 0b101 */
- (msti & 0xfff);
+ 0 << 15 | /* Read */
+ 5 << 12 | /* Table type 0b101 */
+ (msti & 0xfff);
priv->r->exec_tbl0_cmd(cmd);
for (int i = 0; i < 4; i++)
static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
{
u32 cmd = 1 << 16 | /* Execute cmd */
- 1 << 15 | /* Write */
- 5 << 12 | /* Table type 0b101 */
- (msti & 0xfff);
+ 1 << 15 | /* Write */
+ 5 << 12 | /* Table type 0b101 */
+ (msti & 0xfff);
for (int i = 0; i < 4; i++)
sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
priv->r->exec_tbl0_cmd(cmd);
static void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
{
u32 cmd = 1 << 17 | /* Execute cmd */
- 0 << 16 | /* Read */
- 4 << 12 | /* Table type 0b10 */
- (msti & 0xfff);
+ 0 << 16 | /* Read */
+ 4 << 12 | /* Table type 0b10 */
+ (msti & 0xfff);
priv->r->exec_tbl0_cmd(cmd);
for (int i = 0; i < 2; i++)
static void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
{
u32 cmd = 1 << 17 | /* Execute cmd */
- 1 << 16 | /* Write */
- 4 << 12 | /* Table type 4 */
- (msti & 0xfff);
+ 1 << 16 | /* Write */
+ 4 << 12 | /* Table type 4 */
+ (msti & 0xfff);
for (int i = 0; i < 2; i++)
sw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i));
{
u32 k0, k1, h1, h2, h;
- k0 = (u32) (((seed >> 55) & 0x1f) ^
- ((seed >> 44) & 0x7ff) ^
- ((seed >> 33) & 0x7ff) ^
- ((seed >> 22) & 0x7ff) ^
- ((seed >> 11) & 0x7ff) ^
- (seed & 0x7ff));
+ k0 = (u32)(((seed >> 55) & 0x1f) ^
+ ((seed >> 44) & 0x7ff) ^
+ ((seed >> 33) & 0x7ff) ^
+ ((seed >> 22) & 0x7ff) ^
+ ((seed >> 11) & 0x7ff) ^
+ (seed & 0x7ff));
h1 = (seed >> 11) & 0x7ff;
h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
h2 = (seed >> 33) & 0x7ff;
h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);
- k1 = (u32) (((seed << 55) & 0x1f) ^
- ((seed >> 44) & 0x7ff) ^
- h2 ^
- ((seed >> 22) & 0x7ff) ^
- h1 ^
- (seed & 0x7ff));
+ k1 = (u32)(((seed << 55) & 0x1f) ^
+ ((seed >> 44) & 0x7ff) ^
+ h2 ^
+ ((seed >> 22) & 0x7ff) ^
+ h1 ^
+ (seed & 0x7ff));
/* Algorithm choice for block 0 */
if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
u32 k0, k1, h1, h2, h;
k0 = (u32) (((seed >> 55) & 0x1f) ^
- ((seed >> 44) & 0x7ff) ^
- ((seed >> 33) & 0x7ff) ^
- ((seed >> 22) & 0x7ff) ^
- ((seed >> 11) & 0x7ff) ^
- (seed & 0x7ff));
+ ((seed >> 44) & 0x7ff) ^
+ ((seed >> 33) & 0x7ff) ^
+ ((seed >> 22) & 0x7ff) ^
+ ((seed >> 11) & 0x7ff) ^
+ (seed & 0x7ff));
h1 = (seed >> 11) & 0x7ff;
h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x3f);
k1 = (u32) (((seed << 55) & 0x1f) ^
- ((seed >> 44) & 0x7ff) ^
- h2 ^
- ((seed >> 22) & 0x7ff) ^
- h1 ^
- (seed & 0x7ff));
+ ((seed >> 44) & 0x7ff) ^
+ h2 ^
+ ((seed >> 22) & 0x7ff) ^
+ h1 ^
+ (seed & 0x7ff));
/* Algorithm choice for block 0 */
if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
// rows[10] = (HASH_PICK(ip6->s6_addr[10], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[11], 4, 4);
// if (!algorithm) {
// rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5) |
-// (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
+// (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
// rows[12] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) |
-// (HASH_PICK(ip6->s6_addr[13], 2, 6) << 0);
+// (HASH_PICK(ip6->s6_addr[13], 2, 6) << 0);
// rows[13] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) |
-// (HASH_PICK(ip6->s6_addr[14], 1, 7) << 0);
+// (HASH_PICK(ip6->s6_addr[14], 1, 7) << 0);
// if (!move_dip) {
// rows[14] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) |
-// (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
+// (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
// }
// hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^
// rows[5] ^ rows[6] ^ rows[7] ^ rows[8] ^ rows[9] ^
// rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5);
// rows[12] = (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
// rows[13] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) |
-// HASH_PICK(ip6->s6_addr[13], 2, 6);
+// HASH_PICK(ip6->s6_addr[13], 2, 6);
// rows[14] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) |
-// HASH_PICK(ip6->s6_addr[14], 1, 7);
+// HASH_PICK(ip6->s6_addr[14], 1, 7);
// if (!move_dip) {
// rows[15] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) |
-// (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
+// (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
// }
// s0 = rows[12] + rows[13] + rows[14];
// s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);
m->vid_mask = w & 0xfff;
m->action = sw_r32(rtl_table_data(r, 6)) & 0x7;
m->mac_mask = ((((u64)sw_r32(rtl_table_data(r, 5))) << 32) & 0xffffffffffffULL) |
- (sw_r32(rtl_table_data(r, 4)));
+ (sw_r32(rtl_table_data(r, 4)));
m->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL) |
- (sw_r32(rtl_table_data(r, 2)));
+ (sw_r32(rtl_table_data(r, 2)));
/* Bits L3_INTF and BMSK_L3_INTF are 0 */
out:
profile[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(index));
profile[1] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 4) & 0x1FFFFFFFULL) << 32 |
- (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 8) & 0xFFFFFFFF);
+ (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 8) & 0xFFFFFFFF);
profile[2] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 16) & 0x1FFFFFFFULL) << 32 |
- (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 12) & 0xFFFFFFFF);
+ (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 12) & 0xFFFFFFFF);
profile[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20) & 0x1FFFFFFFULL) << 32 |
- (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF);
+ (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF);
pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, \
IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx",
static void rtl931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
{
u32 cmd = 1 << 20 | /* Execute cmd */
- 0 << 19 | /* Read */
- 5 << 15 | /* Table type 0b101 */
- (msti & 0x3fff);
+ 0 << 19 | /* Read */
+ 5 << 15 | /* Table type 0b101 */
+ (msti & 0x3fff);
priv->r->exec_tbl0_cmd(cmd);
for (int i = 0; i < 4; i++)
static void rtl931x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
{
u32 cmd = 1 << 20 | /* Execute cmd */
- 1 << 19 | /* Write */
- 5 << 15 | /* Table type 0b101 */
- (msti & 0x3fff);
+ 1 << 19 | /* Write */
+ 5 << 15 | /* Table type 0b101 */
+ (msti & 0x3fff);
for (int i = 0; i < 4; i++)
sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
priv->r->exec_tbl0_cmd(cmd);
/* TODO: We need a second PIE rule to count the bytes */
flow_stats_update(&cls_flower->stats, 100 * new_packets, new_packets, 0, lastused,
- FLOW_ACTION_HW_STATS_IMMEDIATE);
+ FLOW_ACTION_HW_STATS_IMMEDIATE);
return 0;
}
const struct fdb_update_work *uw = container_of(work, struct fdb_update_work, work);
for (int i = 0; uw->macs[i]; i++) {
- struct switchdev_notifier_fdb_info info;
- u8 addr[ETH_ALEN];
- int action;
+ struct switchdev_notifier_fdb_info info;
+ u8 addr[ETH_ALEN];
+ int action;
action = (uw->macs[i] & (1ULL << 63)) ?
- SWITCHDEV_FDB_ADD_TO_BRIDGE :
- SWITCHDEV_FDB_DEL_TO_BRIDGE;
+ SWITCHDEV_FDB_ADD_TO_BRIDGE :
+ SWITCHDEV_FDB_DEL_TO_BRIDGE;
u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
info.addr = &addr[0];
info.vid = 0;
static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
{
struct notify_b *nb = priv->membase + sizeof(struct ring_b);
- u32 e = priv->lastEvent;
+ u32 e = priv->lastEvent;
while (!(nb->ring[e] & 1)) {
- struct fdb_update_work *w;
- struct n_event *event;
- u64 mac;
- int i;
+ struct fdb_update_work *w;
+ struct n_event *event;
+ u64 mac;
+ int i;
w = kzalloc(sizeof(*w), GFP_ATOMIC);
if (!w) {
/* RX buffer overrun */
if (status_rx_r) {
pr_debug("RX buffer overrun: status %x, mask: %x\n",
- status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk));
+ status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk));
sw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts);
}
sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i));
sw_w32_mask(0x3ff << pos, priv->rxringlen,
- priv->r->dma_if_rx_ring_cntr(i));
+ priv->r->dma_if_rx_ring_cntr(i));
}
}
static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring)
{
for (int i = 0; i < priv->rxrings; i++) {
- struct p_hdr *h;
- int j;
+ struct p_hdr *h;
+ int j;
for (j = 0; j < priv->rxringlen; j++) {
h = &ring->rx_header[i][j];
memset(h, 0, sizeof(struct p_hdr));
h->buf = (u8 *)KSEG1ADDR(ring->rx_space +
- i * priv->rxringlen * RING_BUFFER +
- j * RING_BUFFER);
+ i * priv->rxringlen * RING_BUFFER +
+ j * RING_BUFFER);
h->size = RING_BUFFER;
/* All rings owned by switch, last one wraps */
ring->rx_r[i][j] = KSEG1ADDR(h) | 1 | (j == (priv->rxringlen - 1) ?
- WRAP :
- 0);
+ WRAP :
+ 0);
}
ring->c_rx[i] = 0;
}
h = &ring->tx_header[i][j];
memset(h, 0, sizeof(struct p_hdr));
h->buf = (u8 *)KSEG1ADDR(ring->tx_space +
- i * TXRINGLEN * RING_BUFFER +
- j * RING_BUFFER);
+ i * TXRINGLEN * RING_BUFFER +
+ j * RING_BUFFER);
h->size = RING_BUFFER;
ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);
}
h->size = RING_BUFFER;
ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1 | (ring->c_rx[r] == (priv->rxringlen - 1) ?
- WRAP :
- 0x1);
+ WRAP :
+ 0x1);
ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
} while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);
/* Allocate buffer memory */
priv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER +
- sizeof(struct ring_b) + sizeof(struct notify_b),
- (void *)&dev->mem_start, GFP_KERNEL);
+ sizeof(struct ring_b) + sizeof(struct notify_b),
+ (void *)&dev->mem_start, GFP_KERNEL);
if (!priv->membase) {
dev_err(&pdev->dev, "cannot allocate DMA buffer\n");
return -ENOMEM;
#define RTMDIO_931X_FAMILY_ID 0x9310
/* Register base */
-#define RTMDIO_SW_BASE ((volatile void *) 0xBB000000)
+#define RTMDIO_SW_BASE ((volatile void *) 0xBB000000)
/* MDIO bus registers */
#define RTMDIO_838X_SMI_GLB_CTRL (0xa100)
#define RTMDIO_839X_MODEL_NAME_INFO_REG (0x0ff0)
#define RTMDIO_93XX_MODEL_NAME_INFO_REG (0x0004)
-#define sw_r32(reg) readl(RTMDIO_SW_BASE + reg)
-#define sw_w32(val, reg) writel(val, RTMDIO_SW_BASE + reg)
+#define sw_r32(reg) readl(RTMDIO_SW_BASE + reg)
+#define sw_w32(val, reg) writel(val, RTMDIO_SW_BASE + reg)
#define sw_w32_mask(clear, set, reg) sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
int rtmdio_930x_read_sds_phy(int sds, int page, int regnum);
int rtmdio_930x_read_sds_phy(int sds, int page, int regnum)
{
- int i, ret = -EIO;
- u32 cmd;
+ int i, ret = -EIO;
+ u32 cmd;
if (sds < 0 || sds > 11 || page < 0 || page > 63 || regnum < 0 || regnum > 31)
return -EIO;
mdelay(1);
}
- if (i < 100)
+ if (i < 100)
ret = sw_r32(RTMDIO_930X_SDS_INDACS_DATA) & 0xffff;
mutex_unlock(&rtmdio_lock_sds);
fgcal_binary = rtpcs_sds_read_bits(ctrl, sds_num, 0x1f, 0x14, 5, 0);
pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
- __func__, fgcal_gray, fgcal_binary);
+ __func__, fgcal_gray, fgcal_binary);
offset_range = rtpcs_sds_read_bits(ctrl, sds_num, 0x2e, 0x15, 15, 14);
evenSds = sds - lane;
pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d sds %d\n",
- __func__, cmu_type, cmu_page, frc_cmu_spd, lane, sds);
+ __func__, cmu_type, cmu_page, frc_cmu_spd, lane, sds);
if (cmu_type == 1) {
pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtpcs_sds_read(ctrl, sds, 0x28, 0x7));
}
pr_info("%s: 2.5gbit %08X", __func__,
- rtpcs_sds_read(ctrl, sds, 0x41, 0x14));
+ rtpcs_sds_read(ctrl, sds, 0x41, 0x14));
regmap_read(ctrl->map, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR, &ori);
pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, ori);
break;
case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR / MII_10GR1000BX_AUTO: */
- /* configure 10GR fiber mode=1 */
+ /* configure 10GR fiber mode=1 */
rtpcs_sds_write_bits(ctrl, sds, 0x1f, 0xb, 1, 1, 1);
/* init fiber_1g */
case PHY_INTERFACE_MODE_QSGMII:
default:
pr_info("%s: PHY mode %s not supported by SerDes %d\n",
- __func__, phy_modes(mode), sds);
+ __func__, phy_modes(mode), sds);
return -ENOTSUPP;
}
phydev_info(phydev, "patch chip revision %d\n", val);
for (int i = 0; rtl8380_rtl8218b_perchip[i * 3] &&
- rtl8380_rtl8218b_perchip[i * 3 + 1]; i++) {
+ rtl8380_rtl8218b_perchip[i * 3 + 1]; i++) {
patchphy = get_package_phy(phydev, rtl8380_rtl8218b_perchip[i * 3]);
phy_write_paged(patchphy, RTL838X_PAGE_RAW,
rtl8380_rtl8218b_perchip[i * 3 + 1],
for (int i = 0; rtl8218B_6276B_rtl8380_perport[i * 2]; i++) {
phy_write_paged(phydev, RTL838X_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2],
- rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
+ rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
}
/* Disable broadcast ID */
phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
for (int i = 0; rtl8380_rtl8214fc_perchip[i * 3] &&
- rtl8380_rtl8214fc_perchip[i * 3 + 1]; i++) {
+ rtl8380_rtl8214fc_perchip[i * 3 + 1]; i++) {
u32 page = 0;
if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
for (int i = 0; rtl8380_rtl8214fc_perport[i * 2]; i++) {
phy_write_paged(phydev, RTL838X_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2],
- rtl8380_rtl8214fc_perport[i * 2 + 1]);
+ rtl8380_rtl8214fc_perport[i * 2 + 1]);
}
/* Disable broadcast ID */
#define RTL9300_SAMPLE_DLY_SHIFT (16)
#define RTL9300_SAMPLE_DLY_MASK GENMASK(RTL9300_SAMPLE_DLY_SHIFT + 15, RTL9300_SAMPLE_DLY_SHIFT)
#define RTL9300_COMPARE_DLY_SHIFT (0)
-#define RTL9300_COMPARE_DLY_MASK GENMASK(RTL9300_COMPARE_DLY_SHIFT + 15, RTL9300_COMPARE_DLY_SHIFT)
+#define RTL9300_COMPARE_DLY_MASK GENMASK(RTL9300_COMPARE_DLY_SHIFT + 15, RTL9300_COMPARE_DLY_SHIFT)
struct realtek_thermal_priv {
struct regmap *regmap;
# target device starting from this address.
# KERNEL_IMG_OUT: The filename of the kernel image with the rt-loader prepended.
# If not given it will be created as image.bin into the BUILD_DIR.
-# BUILD_DIR: The temporary build dir. If not given it will be set to "build".
+# BUILD_DIR: The temporary build dir. If not given it will be set to "build".
#
# To add it into the OpenWrt toolchain just create the following new build commands
#
LDFLAGS = -static -nostdlib -T linker/linker.ld --no-warn-mismatch
-O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
+O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
SOURCES = src/startup.S src/main.c src/board.c src/memory.c src/unlzma.c
BUILD_DIR ?= build
IMAGE_OBJ := $(BUILD_DIR)/image.o
-IMAGE_ELF := $(BUILD_DIR)/image.elf
+IMAGE_ELF := $(BUILD_DIR)/image.elf
KERNEL_IMG_NONE := $(BUILD_DIR)/empty_kernel.bin
KERNEL_IMG_IN ?= $(KERNEL_IMG_NONE)
# Setup heap. It will start directly behind BSS
- addiu $t3, MEMORY_ALIGNMENT
+ addiu $t3, MEMORY_ALIGNMENT
li $t4, ~(MEMORY_ALIGNMENT - 1)
and $t3, $t4
projects / openwrt / staging / stintel.git / commitdiff