"target/omap":
- "target/linux/omap/**"
- "package/boot/uboot-omap/**"
-"target/oxnas":
- - "target/linux/oxnas/**"
- - "package/boot/uboot-oxnas/**"
"target/pistachio":
- "target/linux/pistachio/**"
"target/qoriq":
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_VERSION:=2014.10
-PKG_RELEASE:=16
-
-PKG_HASH:=d3b132a7a9b3f3182b7aad71c2dfbd4fc15bea83e12c76134eb3ffefc07d1c71
-
-include $(INCLUDE_DIR)/u-boot.mk
-include $(INCLUDE_DIR)/package.mk
-
-define U-Boot/Default
- BUILD_TARGET:=oxnas
- BUILD_DEVICES:=Default
- HIDDEN:=y
-endef
-
-define U-Boot/ox820
- NAME:=Oxford/PLX NAS7820
-endef
-
-UBOOT_TARGETS:=ox820
-
-define Build/InstallDev
- $(INSTALL_DIR) $(STAGING_DIR_IMAGE)
- $(CP) $(PKG_BUILD_DIR)/u-boot.bin $(STAGING_DIR_IMAGE)/u-boot.bin
-endef
-
-$(eval $(call BuildPackage/U-Boot))
+++ /dev/null
-From df9fb90120423c4c55b66a5dc09af23f605a406b Mon Sep 17 00:00:00 2001
-Date: Mon, 1 Dec 2014 21:37:25 +0100
-Subject: [PATCH] disk/part.c: use unsigned format when printing capacity
-
-Large disks otherwise produce highly unplausible output such as
- Capacity: 1907729.0 MB = 1863.0 GB (-387938128 x 512)
-
-As supposedly all size-related decimals are unsigned, use unsigned
-format in printf statement, resulting in a correct capacity being
-displayed:
- Capacity: 1907729.0 MB = 1863.0 GB (3907029168 x 512)
-
----
- disk/part.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/disk/part.c
-+++ b/disk/part.c
-@@ -229,13 +229,13 @@ void dev_print (block_dev_desc_t *dev_de
- printf (" Supports 48-bit addressing\n");
- #endif
- #if defined(CONFIG_SYS_64BIT_LBA)
-- printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%Ld x %ld)\n",
-+ printf (" Capacity: %lu.%lu MB = %lu.%lu GB (%Lu x %lu)\n",
- mb_quot, mb_rem,
- gb_quot, gb_rem,
- lba,
- dev_desc->blksz);
- #else
-- printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\n",
-+ printf (" Capacity: %lu.%lu MB = %lu.%lu GB (%lu x %lu)\n",
- mb_quot, mb_rem,
- gb_quot, gb_rem,
- (ulong)lba,
+++ /dev/null
---- a/tools/socfpgaimage.c
-+++ b/tools/socfpgaimage.c
-@@ -74,12 +74,12 @@ static uint16_t hdr_checksum(struct socf
- static void build_header(uint8_t *buf, uint8_t version, uint8_t flags,
- uint16_t length_bytes)
- {
-- header.validation = htole32(VALIDATION_WORD);
-+ header.validation = cpu_to_le32(VALIDATION_WORD);
- header.version = version;
- header.flags = flags;
-- header.length_u32 = htole16(length_bytes/4);
-+ header.length_u32 = cpu_to_le16(length_bytes/4);
- header.zero = 0;
-- header.checksum = htole16(hdr_checksum(&header));
-+ header.checksum = cpu_to_le16(hdr_checksum(&header));
-
- memcpy(buf, &header, sizeof(header));
- }
-@@ -92,12 +92,12 @@ static int verify_header(const uint8_t *
- {
- memcpy(&header, buf, sizeof(header));
-
-- if (le32toh(header.validation) != VALIDATION_WORD)
-+ if (le32_to_cpu(header.validation) != VALIDATION_WORD)
- return -1;
-- if (le16toh(header.checksum) != hdr_checksum(&header))
-+ if (le16_to_cpu(header.checksum) != hdr_checksum(&header))
- return -1;
-
-- return le16toh(header.length_u32) * 4;
-+ return le16_to_cpu(header.length_u32) * 4;
- }
-
- /* Sign the buffer and return the signed buffer size */
-@@ -116,7 +116,7 @@ static int sign_buffer(uint8_t *buf,
- /* Calculate and apply the CRC */
- calc_crc = ~pbl_crc32(0, (char *)buf, len);
-
-- *((uint32_t *)(buf + len)) = htole32(calc_crc);
-+ *((uint32_t *)(buf + len)) = cpu_to_le32(calc_crc);
-
- if (!pad_64k)
- return len + 4;
-@@ -150,7 +150,7 @@ static int verify_buffer(const uint8_t *
-
- calc_crc = ~pbl_crc32(0, (const char *)buf, len);
-
-- buf_crc = le32toh(*((uint32_t *)(buf + len)));
-+ buf_crc = le32_to_cpu(*((uint32_t *)(buf + len)));
-
- if (buf_crc != calc_crc) {
- fprintf(stderr, "CRC32 does not match (%08x != %08x)\n",
+++ /dev/null
---- a/common/spl/Makefile
-+++ b/common/spl/Makefile
-@@ -19,4 +19,5 @@ obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc
- obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
- obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
- obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o
-+obj-$(CONFIG_SPL_BLOCK_SUPPORT) += spl_block.o
- endif
---- a/common/spl/spl.c
-+++ b/common/spl/spl.c
-@@ -191,6 +191,14 @@ void board_init_r(gd_t *dummy1, ulong du
- spl_spi_load_image();
- break;
- #endif
-+#ifdef CONFIG_SPL_BLOCK_SUPPORT
-+ case BOOT_DEVICE_BLOCK:
-+ {
-+ extern void spl_block_load_image(void);
-+ spl_block_load_image();
-+ break;
-+ }
-+#endif
- #ifdef CONFIG_SPL_ETH_SUPPORT
- case BOOT_DEVICE_CPGMAC:
- #ifdef CONFIG_SPL_ETH_DEVICE
---- a/common/cmd_nvedit.c
-+++ b/common/cmd_nvedit.c
-@@ -49,6 +49,7 @@ DECLARE_GLOBAL_DATA_PTR;
- !defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \
- !defined(CONFIG_ENV_IS_IN_REMOTE) && \
- !defined(CONFIG_ENV_IS_IN_UBI) && \
-+ !defined(CONFIG_ENV_IS_IN_EXT4) && \
- !defined(CONFIG_ENV_IS_NOWHERE)
- # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
- SPI_FLASH|NVRAM|MMC|FAT|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
---- a/common/Makefile
-+++ b/common/Makefile
-@@ -63,6 +63,7 @@ obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_o
- obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
- obj-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
- obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
-+obj-$(CONFIG_ENV_IS_IN_EXT4) += env_ext4.o
- obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
-
- # command
-@@ -213,6 +214,8 @@ obj-$(CONFIG_UPDATE_TFTP) += update.o
- obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
- obj-$(CONFIG_CMD_DFU) += cmd_dfu.o
- obj-$(CONFIG_CMD_GPT) += cmd_gpt.o
-+else
-+obj-$(CONFIG_SPL_BLOCK_SUPPORT) += cmd_ide.o
- endif
-
- ifdef CONFIG_SPL_BUILD
+++ /dev/null
-From e719404ee1241af679a51879eaad291bc27e4817 Mon Sep 17 00:00:00 2001
-Date: Tue, 2 Dec 2014 14:46:05 +0100
-Subject: [PATCH] net/phy: add back icplus driver
-
-IC+ phy driver was removed due to the lack of users some time ago.
-Add it back, so we can use it.
----
- drivers/net/phy/Makefile | 1 +
- drivers/net/phy/icplus.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++
- drivers/net/phy/phy.c | 3 ++
- 3 files changed, 84 insertions(+)
- create mode 100644 drivers/net/phy/icplus.c
-
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_ATHEROS) += atheros.o
- obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
- obj-$(CONFIG_PHY_DAVICOM) += davicom.o
- obj-$(CONFIG_PHY_ET1011C) += et1011c.o
-+obj-$(CONFIG_PHY_ICPLUS) += icplus.o
- obj-$(CONFIG_PHY_LXT) += lxt.o
- obj-$(CONFIG_PHY_MARVELL) += marvell.o
- obj-$(CONFIG_PHY_MICREL) += micrel.o
---- /dev/null
-+++ b/drivers/net/phy/icplus.c
-@@ -0,0 +1,93 @@
-+/*
-+ * ICPlus PHY drivers
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ *
-+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
-+ */
-+#include <phy.h>
-+
-+/* IP101A/G - IP1001 */
-+#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
-+#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
-+#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
-+#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
-+#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
-+#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
-+#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */
-+#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED
-+#define IP1001LF_DRIVE_MASK (15 << 5)
-+#define IP1001LF_RXCLKDRIVE_HI (2 << 5)
-+#define IP1001LF_RXDDRIVE_HI (2 << 7)
-+#define IP1001LF_RXCLKDRIVE_M (1 << 5)
-+#define IP1001LF_RXDDRIVE_M (1 << 7)
-+#define IP1001LF_RXCLKDRIVE_L (0 << 5)
-+#define IP1001LF_RXDDRIVE_L (0 << 7)
-+#define IP1001LF_RXCLKDRIVE_VL (3 << 5)
-+#define IP1001LF_RXDDRIVE_VL (3 << 7)
-+
-+static int ip1001_config(struct phy_device *phydev)
-+{
-+ int c;
-+
-+ /* Enable Auto Power Saving mode */
-+ c = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2);
-+ if (c < 0)
-+ return c;
-+ c |= IP1001_APS_ON;
-+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c);
-+ if (c < 0)
-+ return c;
-+
-+ /* INTR pin used: speed/link/duplex will cause an interrupt */
-+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS,
-+ IP101A_G_IRQ_DEFAULT);
-+ if (c < 0)
-+ return c;
-+
-+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
-+ /*
-+ * Additional delay (2ns) used to adjust RX clock phase
-+ * at RGMII interface
-+ */
-+ c = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS);
-+ if (c < 0)
-+ return c;
-+
-+ c |= IP1001_PHASE_SEL_MASK;
-+ /* adjust digtial drive strength */
-+ c &= ~IP1001LF_DRIVE_MASK;
-+ c |= IP1001LF_RXCLKDRIVE_M;
-+ c |= IP1001LF_RXDDRIVE_M;
-+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS,
-+ c);
-+ if (c < 0)
-+ return c;
-+ }
-+
-+ return 0;
-+}
-+
-+static int ip1001_startup(struct phy_device *phydev)
-+{
-+ genphy_update_link(phydev);
-+ genphy_parse_link(phydev);
-+
-+ return 0;
-+}
-+static struct phy_driver IP1001_driver = {
-+ .name = "ICPlus IP1001",
-+ .uid = 0x02430d90,
-+ .mask = 0x0ffffff0,
-+ .features = PHY_GBIT_FEATURES,
-+ .config = &ip1001_config,
-+ .startup = &ip1001_startup,
-+ .shutdown = &genphy_shutdown,
-+};
-+
-+int phy_icplus_init(void)
-+{
-+ phy_register(&IP1001_driver);
-+
-+ return 0;
-+}
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -454,6 +454,9 @@ int phy_init(void)
- #ifdef CONFIG_PHY_ET1011C
- phy_et1011c_init();
- #endif
-+#ifdef CONFIG_PHY_ICPLUS
-+ phy_icplus_init();
-+#endif
- #ifdef CONFIG_PHY_LXT
- phy_lxt_init();
- #endif
---- a/include/phy.h
-+++ b/include/phy.h
-@@ -225,6 +225,7 @@ int phy_atheros_init(void);
- int phy_broadcom_init(void);
- int phy_davicom_init(void);
- int phy_et1011c_init(void);
-+int phy_icplus_init(void);
- int phy_lxt_init(void);
- int phy_marvell_init(void);
- int phy_micrel_init(void);
+++ /dev/null
---- a/arch/arm/include/asm/mach-types.h
-+++ b/arch/arm/include/asm/mach-types.h
-@@ -212,6 +212,7 @@ extern unsigned int __machine_arch_type;
- #define MACH_TYPE_EDB9307A 1128
- #define MACH_TYPE_OMAP_3430SDP 1138
- #define MACH_TYPE_VSTMS 1140
-+#define MACH_TYPE_OXNAS 1152
- #define MACH_TYPE_MICRO9M 1169
- #define MACH_TYPE_BUG 1179
- #define MACH_TYPE_AT91SAM9263EK 1202
---- a/drivers/block/Makefile
-+++ b/drivers/block/Makefile
-@@ -21,3 +21,4 @@ obj-$(CONFIG_IDE_SIL680) += sil680.o
- obj-$(CONFIG_SANDBOX) += sandbox.o
- obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
- obj-$(CONFIG_SYSTEMACE) += systemace.o
-+obj-$(CONFIG_IDE_PLX) += plxsata_ide.o
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
- obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
- obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
- obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
-+obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o
- obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
- obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
- obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
---- a/tools/.gitignore
-+++ b/tools/.gitignore
-@@ -9,6 +9,7 @@
- /mkenvimage
- /mkimage
- /mkexynosspl
-+/mkox820crc
- /mpc86x_clk
- /mxsboot
- /mksunxiboot
---- a/tools/Makefile
-+++ b/tools/Makefile
-@@ -143,6 +143,12 @@ hostprogs-$(CONFIG_KIRKWOOD) += kwboot
- hostprogs-y += proftool
- hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela
-
-+
-+hostprogs-$(CONFIG_OX820) += mkox820crc$(SFX)
-+
-+mkox820crc$(SFX)-objs := mkox820crc.o lib/crc32.o
-+
-+
- # We build some files with extra pedantic flags to try to minimize things
- # that won't build on some weird host compiler -- though there are lots of
- # exceptions for files that aren't complaint.
---- a/drivers/serial/ns16550.c
-+++ b/drivers/serial/ns16550.c
-@@ -118,6 +118,14 @@ int ns16550_calc_divisor(NS16550_t port,
- }
- port->osc_12m_sel = 0; /* clear if previsouly set */
- #endif
-+#ifdef CONFIG_OX820
-+ {
-+ /* with additional 3 bit fractional */
-+ u32 div = (CONFIG_SYS_NS16550_CLK + baudrate) / (baudrate * 2);
-+ port->reg9 = (div & 7) << 5;
-+ return (div >> 3);
-+ }
-+#endif
-
- return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
- }
---- a/scripts/Makefile.spl
-+++ b/scripts/Makefile.spl
-@@ -202,6 +202,9 @@ OBJCOPYFLAGS_$(SPL_BIN).bin = $(SPL_OBJC
-
- $(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN) FORCE
- $(call if_changed,objcopy)
-+ifdef CONFIG_OX820
-+ $(OBJTREE)/tools/mkox820crc $@
-+endif
-
- LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
- ifneq ($(CONFIG_SPL_TEXT_BASE),)
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -488,6 +488,9 @@ config TARGET_BALLOON3
- config TARGET_H2200
- bool "Support h2200"
-
-+config TARGET_OX820
-+ bool "Support ox820"
-+
- config TARGET_PALMLD
- bool "Support palmld"
-
-@@ -650,6 +653,7 @@ source "board/logicpd/imx27lite/Kconfig"
- source "board/logicpd/imx31_litekit/Kconfig"
- source "board/mpl/vcma9/Kconfig"
- source "board/olimex/mx23_olinuxino/Kconfig"
-+source "board/ox820/Kconfig"
- source "board/palmld/Kconfig"
- source "board/palmtc/Kconfig"
- source "board/palmtreo680/Kconfig"
+++ /dev/null
-Date: Sat, 7 Feb 2015 21:52:40 +0000 (+0100)
-Subject: Add linux/compiler-gcc5.h to fix builds with gcc5
-X-Git-Tag: v2015.04-rc2~31
-X-Git-Url: http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=478b02f1a7043b673565075ea5016376f3293b23
-
-Add linux/compiler-gcc5.h to fix builds with gcc5
-
-Add linux/compiler-gcc5/h from the kernel sources at:
-
-commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b
-Date: Sat Oct 25 15:09:42 2014 -0700
-
- compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles
-
----
-
---- /dev/null
-+++ b/include/linux/compiler-gcc5.h
-@@ -0,0 +1,65 @@
-+#ifndef __LINUX_COMPILER_H
-+#error "Please don't include <linux/compiler-gcc5.h> directly, include <linux/compiler.h> instead."
-+#endif
-+
-+#define __used __attribute__((__used__))
-+#define __must_check __attribute__((warn_unused_result))
-+#define __compiler_offsetof(a, b) __builtin_offsetof(a, b)
-+
-+/* Mark functions as cold. gcc will assume any path leading to a call
-+ to them will be unlikely. This means a lot of manual unlikely()s
-+ are unnecessary now for any paths leading to the usual suspects
-+ like BUG(), printk(), panic() etc. [but let's keep them for now for
-+ older compilers]
-+
-+ Early snapshots of gcc 4.3 don't support this and we can't detect this
-+ in the preprocessor, but we can live with this because they're unreleased.
-+ Maketime probing would be overkill here.
-+
-+ gcc also has a __attribute__((__hot__)) to move hot functions into
-+ a special section, but I don't see any sense in this right now in
-+ the kernel context */
-+#define __cold __attribute__((__cold__))
-+
-+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-+
-+#ifndef __CHECKER__
-+# define __compiletime_warning(message) __attribute__((warning(message)))
-+# define __compiletime_error(message) __attribute__((error(message)))
-+#endif /* __CHECKER__ */
-+
-+/*
-+ * Mark a position in code as unreachable. This can be used to
-+ * suppress control flow warnings after asm blocks that transfer
-+ * control elsewhere.
-+ *
-+ * Early snapshots of gcc 4.5 don't support this and we can't detect
-+ * this in the preprocessor, but we can live with this because they're
-+ * unreleased. Really, we need to have autoconf for the kernel.
-+ */
-+#define unreachable() __builtin_unreachable()
-+
-+/* Mark a function definition as prohibited from being cloned. */
-+#define __noclone __attribute__((__noclone__))
-+
-+/*
-+ * Tell the optimizer that something else uses this function or variable.
-+ */
-+#define __visible __attribute__((externally_visible))
-+
-+/*
-+ * GCC 'asm goto' miscompiles certain code sequences:
-+ *
-+ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
-+ *
-+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
-+ *
-+ * (asm goto is automatically volatile - the naming reflects this.)
-+ */
-+#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0)
-+
-+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
-+#define __HAVE_BUILTIN_BSWAP32__
-+#define __HAVE_BUILTIN_BSWAP64__
-+#define __HAVE_BUILTIN_BSWAP16__
-+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
+++ /dev/null
-Date: Sat, 7 Feb 2015 21:52:40 +0000 (+0100)
-Subject: Add linux/compiler-gcc6.h to fix builds with gcc6
-X-Git-Tag: v2015.04-rc2~31
-X-Git-Url: http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=478b02f1a7043b673565075ea5016376f3293b23
-
-Add linux/compiler-gcc6.h to fix builds with gcc6
-
-Add linux/compiler-gcc6/h from the kernel sources at:
-
-commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b
-Date: Sat Oct 25 15:09:42 2014 -0700
-
- compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles
-
----
-
---- /dev/null
-+++ b/include/linux/compiler-gcc6.h
-@@ -0,0 +1,284 @@
-+#ifndef __LINUX_COMPILER_H
-+#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
-+#endif
-+
-+/*
-+ * Common definitions for all gcc versions go here.
-+ */
-+#define GCC_VERSION (__GNUC__ * 10000 \
-+ + __GNUC_MINOR__ * 100 \
-+ + __GNUC_PATCHLEVEL__)
-+
-+/* Optimization barrier */
-+
-+/* The "volatile" is due to gcc bugs */
-+#define barrier() __asm__ __volatile__("": : :"memory")
-+/*
-+ * This version is i.e. to prevent dead stores elimination on @ptr
-+ * where gcc and llvm may behave differently when otherwise using
-+ * normal barrier(): while gcc behavior gets along with a normal
-+ * barrier(), llvm needs an explicit input variable to be assumed
-+ * clobbered. The issue is as follows: while the inline asm might
-+ * access any memory it wants, the compiler could have fit all of
-+ * @ptr into memory registers instead, and since @ptr never escaped
-+ * from that, it proofed that the inline asm wasn't touching any of
-+ * it. This version works well with both compilers, i.e. we're telling
-+ * the compiler that the inline asm absolutely may see the contents
-+ * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495
-+ */
-+#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory")
-+
-+/*
-+ * This macro obfuscates arithmetic on a variable address so that gcc
-+ * shouldn't recognize the original var, and make assumptions about it.
-+ *
-+ * This is needed because the C standard makes it undefined to do
-+ * pointer arithmetic on "objects" outside their boundaries and the
-+ * gcc optimizers assume this is the case. In particular they
-+ * assume such arithmetic does not wrap.
-+ *
-+ * A miscompilation has been observed because of this on PPC.
-+ * To work around it we hide the relationship of the pointer and the object
-+ * using this macro.
-+ *
-+ * Versions of the ppc64 compiler before 4.1 had a bug where use of
-+ * RELOC_HIDE could trash r30. The bug can be worked around by changing
-+ * the inline assembly constraint from =g to =r, in this particular
-+ * case either is valid.
-+ */
-+#define RELOC_HIDE(ptr, off) \
-+({ \
-+ unsigned long __ptr; \
-+ __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \
-+ (typeof(ptr)) (__ptr + (off)); \
-+})
-+
-+/* Make the optimizer believe the variable can be manipulated arbitrarily. */
-+#define OPTIMIZER_HIDE_VAR(var) \
-+ __asm__ ("" : "=r" (var) : "0" (var))
-+
-+#ifdef __CHECKER__
-+#define __must_be_array(a) 0
-+#else
-+/* &a[0] degrades to a pointer: a different type from an array */
-+#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
-+#endif
-+
-+/*
-+ * Force always-inline if the user requests it so via the .config,
-+ * or if gcc is too old:
-+ */
-+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
-+ !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
-+#define inline inline __attribute__((always_inline)) notrace
-+#define __inline__ __inline__ __attribute__((always_inline)) notrace
-+#define __inline __inline __attribute__((always_inline)) notrace
-+#else
-+/* A lot of inline functions can cause havoc with function tracing */
-+#define inline inline notrace
-+#define __inline__ __inline__ notrace
-+#define __inline __inline notrace
-+#endif
-+
-+#define __always_inline inline __attribute__((always_inline))
-+#define noinline __attribute__((noinline))
-+
-+#define __deprecated __attribute__((deprecated))
-+#define __packed __attribute__((packed))
-+#define __weak __attribute__((weak))
-+#define __alias(symbol) __attribute__((alias(#symbol)))
-+
-+/*
-+ * it doesn't make sense on ARM (currently the only user of __naked)
-+ * to trace naked functions because then mcount is called without
-+ * stack and frame pointer being set up and there is no chance to
-+ * restore the lr register to the value before mcount was called.
-+ *
-+ * The asm() bodies of naked functions often depend on standard calling
-+ * conventions, therefore they must be noinline and noclone.
-+ *
-+ * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.
-+ * See GCC PR44290.
-+ */
-+#define __naked __attribute__((naked)) noinline __noclone notrace
-+
-+#define __noreturn __attribute__((noreturn))
-+
-+/*
-+ * From the GCC manual:
-+ *
-+ * Many functions have no effects except the return value and their
-+ * return value depends only on the parameters and/or global
-+ * variables. Such a function can be subject to common subexpression
-+ * elimination and loop optimization just as an arithmetic operator
-+ * would be.
-+ * [...]
-+ */
-+#define __pure __attribute__((pure))
-+#define __aligned(x) __attribute__((aligned(x)))
-+#define __printf(a, b) __attribute__((format(printf, a, b)))
-+#define __scanf(a, b) __attribute__((format(scanf, a, b)))
-+#define __attribute_const__ __attribute__((__const__))
-+#define __maybe_unused __attribute__((unused))
-+#define __always_unused __attribute__((unused))
-+
-+/* gcc version specific checks */
-+
-+#if GCC_VERSION < 30200
-+# error Sorry, your compiler is too old - please upgrade it.
-+#endif
-+
-+#if GCC_VERSION < 30300
-+# define __used __attribute__((__unused__))
-+#else
-+# define __used __attribute__((__used__))
-+#endif
-+
-+#ifdef CONFIG_GCOV_KERNEL
-+# if GCC_VERSION < 30400
-+# error "GCOV profiling support for gcc versions below 3.4 not included"
-+# endif /* __GNUC_MINOR__ */
-+#endif /* CONFIG_GCOV_KERNEL */
-+
-+#if GCC_VERSION >= 30400
-+#define __must_check __attribute__((warn_unused_result))
-+#define __malloc __attribute__((__malloc__))
-+#endif
-+
-+#if GCC_VERSION >= 40000
-+
-+/* GCC 4.1.[01] miscompiles __weak */
-+#ifdef __KERNEL__
-+# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101
-+# error Your version of gcc miscompiles the __weak directive
-+# endif
-+#endif
-+
-+#define __used __attribute__((__used__))
-+#define __compiler_offsetof(a, b) \
-+ __builtin_offsetof(a, b)
-+
-+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600
-+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
-+#endif
-+
-+#if GCC_VERSION >= 40300
-+/* Mark functions as cold. gcc will assume any path leading to a call
-+ * to them will be unlikely. This means a lot of manual unlikely()s
-+ * are unnecessary now for any paths leading to the usual suspects
-+ * like BUG(), printk(), panic() etc. [but let's keep them for now for
-+ * older compilers]
-+ *
-+ * Early snapshots of gcc 4.3 don't support this and we can't detect this
-+ * in the preprocessor, but we can live with this because they're unreleased.
-+ * Maketime probing would be overkill here.
-+ *
-+ * gcc also has a __attribute__((__hot__)) to move hot functions into
-+ * a special section, but I don't see any sense in this right now in
-+ * the kernel context
-+ */
-+#define __cold __attribute__((__cold__))
-+
-+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-+
-+#ifndef __CHECKER__
-+# define __compiletime_warning(message) __attribute__((warning(message)))
-+# define __compiletime_error(message) __attribute__((error(message)))
-+#endif /* __CHECKER__ */
-+#endif /* GCC_VERSION >= 40300 */
-+
-+#if GCC_VERSION >= 40500
-+/*
-+ * Mark a position in code as unreachable. This can be used to
-+ * suppress control flow warnings after asm blocks that transfer
-+ * control elsewhere.
-+ *
-+ * Early snapshots of gcc 4.5 don't support this and we can't detect
-+ * this in the preprocessor, but we can live with this because they're
-+ * unreleased. Really, we need to have autoconf for the kernel.
-+ */
-+#define unreachable() __builtin_unreachable()
-+
-+/* Mark a function definition as prohibited from being cloned. */
-+#define __noclone __attribute__((__noclone__, __optimize__("no-tracer")))
-+
-+#endif /* GCC_VERSION >= 40500 */
-+
-+#if GCC_VERSION >= 40600
-+/*
-+ * When used with Link Time Optimization, gcc can optimize away C functions or
-+ * variables which are referenced only from assembly code. __visible tells the
-+ * optimizer that something else uses this function or variable, thus preventing
-+ * this.
-+ */
-+#define __visible __attribute__((externally_visible))
-+#endif
-+
-+
-+#if GCC_VERSION >= 40900 && !defined(__CHECKER__)
-+/*
-+ * __assume_aligned(n, k): Tell the optimizer that the returned
-+ * pointer can be assumed to be k modulo n. The second argument is
-+ * optional (default 0), so we use a variadic macro to make the
-+ * shorthand.
-+ *
-+ * Beware: Do not apply this to functions which may return
-+ * ERR_PTRs. Also, it is probably unwise to apply it to functions
-+ * returning extra information in the low bits (but in that case the
-+ * compiler should see some alignment anyway, when the return value is
-+ * massaged by 'flags = ptr & 3; ptr &= ~3;').
-+ */
-+#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))
-+#endif
-+
-+/*
-+ * GCC 'asm goto' miscompiles certain code sequences:
-+ *
-+ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
-+ *
-+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
-+ *
-+ * (asm goto is automatically volatile - the naming reflects this.)
-+ */
-+#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0)
-+
-+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
-+#if GCC_VERSION >= 40400
-+#define __HAVE_BUILTIN_BSWAP32__
-+#define __HAVE_BUILTIN_BSWAP64__
-+#endif
-+#if GCC_VERSION >= 40800
-+#define __HAVE_BUILTIN_BSWAP16__
-+#endif
-+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
-+
-+#if GCC_VERSION >= 50000
-+#define KASAN_ABI_VERSION 4
-+#elif GCC_VERSION >= 40902
-+#define KASAN_ABI_VERSION 3
-+#endif
-+
-+#if GCC_VERSION >= 40902
-+/*
-+ * Tell the compiler that address safety instrumentation (KASAN)
-+ * should not be applied to that function.
-+ * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
-+ */
-+#define __no_sanitize_address __attribute__((no_sanitize_address))
-+#endif
-+
-+#endif /* gcc version >= 40000 specific checks */
-+
-+#if !defined(__noclone)
-+#define __noclone /* not needed */
-+#endif
-+
-+#if !defined(__no_sanitize_address)
-+#define __no_sanitize_address
-+#endif
-+
-+/*
-+ * A trick to suppress uninitialized variable warning without generating any
-+ * code
-+ */
-+#define uninitialized_var(x) x = x
+++ /dev/null
---- /dev/null
-+++ b/include/linux/compiler-gcc7.h
-@@ -0,0 +1,284 @@
-+#ifndef __LINUX_COMPILER_H
-+#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
-+#endif
-+
-+/*
-+ * Common definitions for all gcc versions go here.
-+ */
-+#define GCC_VERSION (__GNUC__ * 10000 \
-+ + __GNUC_MINOR__ * 100 \
-+ + __GNUC_PATCHLEVEL__)
-+
-+/* Optimization barrier */
-+
-+/* The "volatile" is due to gcc bugs */
-+#define barrier() __asm__ __volatile__("": : :"memory")
-+/*
-+ * This version is i.e. to prevent dead stores elimination on @ptr
-+ * where gcc and llvm may behave differently when otherwise using
-+ * normal barrier(): while gcc behavior gets along with a normal
-+ * barrier(), llvm needs an explicit input variable to be assumed
-+ * clobbered. The issue is as follows: while the inline asm might
-+ * access any memory it wants, the compiler could have fit all of
-+ * @ptr into memory registers instead, and since @ptr never escaped
-+ * from that, it proofed that the inline asm wasn't touching any of
-+ * it. This version works well with both compilers, i.e. we're telling
-+ * the compiler that the inline asm absolutely may see the contents
-+ * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495
-+ */
-+#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory")
-+
-+/*
-+ * This macro obfuscates arithmetic on a variable address so that gcc
-+ * shouldn't recognize the original var, and make assumptions about it.
-+ *
-+ * This is needed because the C standard makes it undefined to do
-+ * pointer arithmetic on "objects" outside their boundaries and the
-+ * gcc optimizers assume this is the case. In particular they
-+ * assume such arithmetic does not wrap.
-+ *
-+ * A miscompilation has been observed because of this on PPC.
-+ * To work around it we hide the relationship of the pointer and the object
-+ * using this macro.
-+ *
-+ * Versions of the ppc64 compiler before 4.1 had a bug where use of
-+ * RELOC_HIDE could trash r30. The bug can be worked around by changing
-+ * the inline assembly constraint from =g to =r, in this particular
-+ * case either is valid.
-+ */
-+#define RELOC_HIDE(ptr, off) \
-+({ \
-+ unsigned long __ptr; \
-+ __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \
-+ (typeof(ptr)) (__ptr + (off)); \
-+})
-+
-+/* Make the optimizer believe the variable can be manipulated arbitrarily. */
-+#define OPTIMIZER_HIDE_VAR(var) \
-+ __asm__ ("" : "=r" (var) : "0" (var))
-+
-+#ifdef __CHECKER__
-+#define __must_be_array(a) 0
-+#else
-+/* &a[0] degrades to a pointer: a different type from an array */
-+#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
-+#endif
-+
-+/*
-+ * Force always-inline if the user requests it so via the .config,
-+ * or if gcc is too old:
-+ */
-+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
-+ !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
-+#define inline inline __attribute__((always_inline)) notrace
-+#define __inline__ __inline__ __attribute__((always_inline)) notrace
-+#define __inline __inline __attribute__((always_inline)) notrace
-+#else
-+/* A lot of inline functions can cause havoc with function tracing */
-+#define inline inline notrace
-+#define __inline__ __inline__ notrace
-+#define __inline __inline notrace
-+#endif
-+
-+#define __always_inline inline __attribute__((always_inline))
-+#define noinline __attribute__((noinline))
-+
-+#define __deprecated __attribute__((deprecated))
-+#define __packed __attribute__((packed))
-+#define __weak __attribute__((weak))
-+#define __alias(symbol) __attribute__((alias(#symbol)))
-+
-+/*
-+ * it doesn't make sense on ARM (currently the only user of __naked)
-+ * to trace naked functions because then mcount is called without
-+ * stack and frame pointer being set up and there is no chance to
-+ * restore the lr register to the value before mcount was called.
-+ *
-+ * The asm() bodies of naked functions often depend on standard calling
-+ * conventions, therefore they must be noinline and noclone.
-+ *
-+ * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.
-+ * See GCC PR44290.
-+ */
-+#define __naked __attribute__((naked)) noinline __noclone notrace
-+
-+#define __noreturn __attribute__((noreturn))
-+
-+/*
-+ * From the GCC manual:
-+ *
-+ * Many functions have no effects except the return value and their
-+ * return value depends only on the parameters and/or global
-+ * variables. Such a function can be subject to common subexpression
-+ * elimination and loop optimization just as an arithmetic operator
-+ * would be.
-+ * [...]
-+ */
-+#define __pure __attribute__((pure))
-+#define __aligned(x) __attribute__((aligned(x)))
-+#define __printf(a, b) __attribute__((format(printf, a, b)))
-+#define __scanf(a, b) __attribute__((format(scanf, a, b)))
-+#define __attribute_const__ __attribute__((__const__))
-+#define __maybe_unused __attribute__((unused))
-+#define __always_unused __attribute__((unused))
-+
-+/* gcc version specific checks */
-+
-+#if GCC_VERSION < 30200
-+# error Sorry, your compiler is too old - please upgrade it.
-+#endif
-+
-+#if GCC_VERSION < 30300
-+# define __used __attribute__((__unused__))
-+#else
-+# define __used __attribute__((__used__))
-+#endif
-+
-+#ifdef CONFIG_GCOV_KERNEL
-+# if GCC_VERSION < 30400
-+# error "GCOV profiling support for gcc versions below 3.4 not included"
-+# endif /* __GNUC_MINOR__ */
-+#endif /* CONFIG_GCOV_KERNEL */
-+
-+#if GCC_VERSION >= 30400
-+#define __must_check __attribute__((warn_unused_result))
-+#define __malloc __attribute__((__malloc__))
-+#endif
-+
-+#if GCC_VERSION >= 40000
-+
-+/* GCC 4.1.[01] miscompiles __weak */
-+#ifdef __KERNEL__
-+# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101
-+# error Your version of gcc miscompiles the __weak directive
-+# endif
-+#endif
-+
-+#define __used __attribute__((__used__))
-+#define __compiler_offsetof(a, b) \
-+ __builtin_offsetof(a, b)
-+
-+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600
-+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
-+#endif
-+
-+#if GCC_VERSION >= 40300
-+/* Mark functions as cold. gcc will assume any path leading to a call
-+ * to them will be unlikely. This means a lot of manual unlikely()s
-+ * are unnecessary now for any paths leading to the usual suspects
-+ * like BUG(), printk(), panic() etc. [but let's keep them for now for
-+ * older compilers]
-+ *
-+ * Early snapshots of gcc 4.3 don't support this and we can't detect this
-+ * in the preprocessor, but we can live with this because they're unreleased.
-+ * Maketime probing would be overkill here.
-+ *
-+ * gcc also has a __attribute__((__hot__)) to move hot functions into
-+ * a special section, but I don't see any sense in this right now in
-+ * the kernel context
-+ */
-+#define __cold __attribute__((__cold__))
-+
-+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-+
-+#ifndef __CHECKER__
-+# define __compiletime_warning(message) __attribute__((warning(message)))
-+# define __compiletime_error(message) __attribute__((error(message)))
-+#endif /* __CHECKER__ */
-+#endif /* GCC_VERSION >= 40300 */
-+
-+#if GCC_VERSION >= 40500
-+/*
-+ * Mark a position in code as unreachable. This can be used to
-+ * suppress control flow warnings after asm blocks that transfer
-+ * control elsewhere.
-+ *
-+ * Early snapshots of gcc 4.5 don't support this and we can't detect
-+ * this in the preprocessor, but we can live with this because they're
-+ * unreleased. Really, we need to have autoconf for the kernel.
-+ */
-+#define unreachable() __builtin_unreachable()
-+
-+/* Mark a function definition as prohibited from being cloned. */
-+#define __noclone __attribute__((__noclone__, __optimize__("no-tracer")))
-+
-+#endif /* GCC_VERSION >= 40500 */
-+
-+#if GCC_VERSION >= 40600
-+/*
-+ * When used with Link Time Optimization, gcc can optimize away C functions or
-+ * variables which are referenced only from assembly code. __visible tells the
-+ * optimizer that something else uses this function or variable, thus preventing
-+ * this.
-+ */
-+#define __visible __attribute__((externally_visible))
-+#endif
-+
-+
-+#if GCC_VERSION >= 40900 && !defined(__CHECKER__)
-+/*
-+ * __assume_aligned(n, k): Tell the optimizer that the returned
-+ * pointer can be assumed to be k modulo n. The second argument is
-+ * optional (default 0), so we use a variadic macro to make the
-+ * shorthand.
-+ *
-+ * Beware: Do not apply this to functions which may return
-+ * ERR_PTRs. Also, it is probably unwise to apply it to functions
-+ * returning extra information in the low bits (but in that case the
-+ * compiler should see some alignment anyway, when the return value is
-+ * massaged by 'flags = ptr & 3; ptr &= ~3;').
-+ */
-+#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))
-+#endif
-+
-+/*
-+ * GCC 'asm goto' miscompiles certain code sequences:
-+ *
-+ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
-+ *
-+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
-+ *
-+ * (asm goto is automatically volatile - the naming reflects this.)
-+ */
-+#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0)
-+
-+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
-+#if GCC_VERSION >= 40400
-+#define __HAVE_BUILTIN_BSWAP32__
-+#define __HAVE_BUILTIN_BSWAP64__
-+#endif
-+#if GCC_VERSION >= 40800
-+#define __HAVE_BUILTIN_BSWAP16__
-+#endif
-+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
-+
-+#if GCC_VERSION >= 50000
-+#define KASAN_ABI_VERSION 4
-+#elif GCC_VERSION >= 40902
-+#define KASAN_ABI_VERSION 3
-+#endif
-+
-+#if GCC_VERSION >= 40902
-+/*
-+ * Tell the compiler that address safety instrumentation (KASAN)
-+ * should not be applied to that function.
-+ * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
-+ */
-+#define __no_sanitize_address __attribute__((no_sanitize_address))
-+#endif
-+
-+#endif /* gcc version >= 40000 specific checks */
-+
-+#if !defined(__noclone)
-+#define __noclone /* not needed */
-+#endif
-+
-+#if !defined(__no_sanitize_address)
-+#define __no_sanitize_address
-+#endif
-+
-+/*
-+ * A trick to suppress uninitialized variable warning without generating any
-+ * code
-+ */
-+#define uninitialized_var(x) x = x
+++ /dev/null
---- a/common/cmd_bootm.c
-+++ b/common/cmd_bootm.c
-@@ -77,7 +77,7 @@ static int do_bootm_subcommand(cmd_tbl_t
- return CMD_RET_USAGE;
- }
-
-- if (state != BOOTM_STATE_START && images.state >= state) {
-+ if (!(state & BOOTM_STATE_START) && images.state >= state) {
- printf("Trying to execute a command out of order\n");
- return CMD_RET_USAGE;
- }
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += reset.o
-obj-y += timer.o
-obj-y += clock.o
-obj-y += pinmux.o
+++ /dev/null
-#include <common.h>
-#include <asm/arch/sysctl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-
-typedef struct {
- unsigned short mhz;
- unsigned char refdiv;
- unsigned char outdiv;
- unsigned int fbdiv;
- unsigned short bwadj;
- unsigned short sfreq;
- unsigned int sslope;
-} PLL_CONFIG;
-
-const PLL_CONFIG C_PLL_CONFIG[] = {
- { 500, 1, 2, 3932160, 119, 208, 189 }, // 500 MHz
- { 525, 2, 1, 4128768, 125, 139, 297 }, // 525 MHz
- { 550, 2, 1, 4325376, 131, 139, 311 }, // 550 MHz
- { 575, 2, 1, 4521984, 137, 139, 326 }, // 575 MHz
- { 600, 2, 1, 4718592, 143, 138, 339 }, // 600 MHz
- { 625, 1, 1, 3276800, 99, 208, 157 }, // 625 MHz
- { 650, 1, 1, 3407872, 103, 208, 164 }, // 650 MHz
- { 675, 1, 1, 3538944, 107, 208, 170 }, // 675 MHz
- { 700, 0, 0, 917504, 27, 416, 22 }, // 700 MHz
- { 725, 1, 1, 3801088, 115, 208, 182 }, // 725 MHz
- { 750, 0, 0, 983040, 29, 416, 23 }, // 750 MHz
- { 775, 3, 0, 4063232, 123, 104, 390 }, // 775 MHz
- { 800, 3, 0, 4194304, 127, 104, 403 }, // 800 MHz
- { 825, 3, 0, 4325376, 131, 104, 415 }, // 825 MHz
- { 850, 2, 0, 3342336, 101, 139, 241 }, // 850 MHz
- { 875, 2, 0, 3440640, 104, 139, 248 }, // 875 MHz
- { 900, 2, 0, 3538944, 107, 139, 255 }, // 900 MHz
- { 925, 2, 0, 3637248, 110, 139, 262 }, // 925 MHz
- { 950, 2, 0, 3735552, 113, 139, 269 }, // 950 MHz
- { 975, 2, 0, 3833856, 116, 139, 276 }, // 975 MHz
- { 1000, 2, 0, 3932160, 119, 139, 283 }, // 1000 MHz
-};
-
-#define PLL_BYPASS (1<<1)
-#define SAT_ENABLE (1<<3)
-
-#define PLL_OUTDIV_SHIFT 4
-#define PLL_REFDIV_SHIFT 8
-#define PLL_BWADJ_SHIFT 16
-
-#define PLL_LOW_FREQ 500
-#define PLL_FREQ_STEP 25
-static void plla_configure(int outdiv, int refdiv, int fbdiv, int bwadj,
- int sfreq, int sslope)
-{
- setbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS);
- udelay(10);
- reset_block(SYS_CTRL_RST_PLLA, 1);
- udelay(10);
-
- writel((refdiv << PLL_REFDIV_SHIFT) | (outdiv << PLL_OUTDIV_SHIFT) |
- SAT_ENABLE | PLL_BYPASS,
- SYS_CTRL_PLLA_CTRL0);
-
- writel(fbdiv, SYS_CTRL_PLLA_CTRL1);
- writel((bwadj << PLL_BWADJ_SHIFT) | sfreq, SYS_CTRL_PLLA_CTRL2);
- writel(sslope, SYS_CTRL_PLLA_CTRL3);
-
- udelay(10); // 5us delay required (from TCI datasheet), use 10us
-
- reset_block(SYS_CTRL_RST_PLLA, 0);
-
- udelay(100); // Delay for PLL to lock
-
- printf(" plla_ctrl0 : %08x\n", readl(SYS_CTRL_PLLA_CTRL0));
- printf(" plla_ctrl1 : %08x\n", readl(SYS_CTRL_PLLA_CTRL1));
- printf(" plla_ctrl2 : %08x\n", readl(SYS_CTRL_PLLA_CTRL2));
- printf(" plla_ctrl3 : %08x\n", readl(SYS_CTRL_PLLA_CTRL3));
-
- clrbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS); // Take PLL out of bypass
- puts("\nPLLA Set\n");
-}
-
-int plla_set_config(int mhz)
-{
- int index = (mhz - PLL_LOW_FREQ) / PLL_FREQ_STEP;
- const PLL_CONFIG *cfg;
-
- if (index < 0 || index > ARRAY_SIZE(C_PLL_CONFIG)) {
- debug("Freq %d MHz out of range, default to lowest\n", mhz);
- index = 0;
- }
- cfg = &C_PLL_CONFIG[index];
-
- printf("Attempting to set PLLA to %d MHz ...\n", (unsigned) cfg->mhz);
- plla_configure(cfg->outdiv, cfg->refdiv, cfg->fbdiv, cfg->bwadj,
- cfg->sfreq, cfg->sslope);
-
- return cfg->mhz;
-}
-
+++ /dev/null
-#include <common.h>
-#include <asm/arch/pinmux.h>
-
-void pinmux_set(int bank, int pin, int func)
-{
- u32 reg;
- u32 base;
- /* TODO: check parameters */
-
- if (bank == PINMUX_BANK_MFA)
- base = SYS_CONTROL_BASE;
- else
- base = SEC_CONTROL_BASE;
-
- clrbits_le32(base + PINMUX_SECONDARY_SEL, BIT(pin));
- clrbits_le32(base + PINMUX_TERTIARY_SEL, BIT(pin));
- clrbits_le32(base + PINMUX_QUATERNARY_SEL, BIT(pin));
- clrbits_le32(base + PINMUX_DEBUG_SEL, BIT(pin));
- clrbits_le32(base + PINMUX_ALTERNATIVE_SEL, BIT(pin));
-
- switch (func) {
- case PINMUX_GPIO:
- default:
- return;
- break;
- case PINMUX_2:
- reg = base + PINMUX_SECONDARY_SEL;
- break;
- case PINMUX_3:
- reg = base + PINMUX_TERTIARY_SEL;
- break;
- case PINMUX_4:
- reg = base + PINMUX_QUATERNARY_SEL;
- break;
- case PINMUX_DEBUG:
- reg = base + PINMUX_DEBUG_SEL;
- break;
- case PINMUX_ALT:
- reg = base + PINMUX_ALTERNATIVE_SEL;
- break;
- }
- setbits_le32(reg, BIT(pin));
-}
+++ /dev/null
-#include <common.h>
-#include <asm/arch/sysctl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/clock.h>
-
-void reset_cpu(ulong addr)
-{
- u32 value;
-
- // Assert reset to cores as per power on defaults
- // Don't touch the DDR interface as things will come to an impromptu stop
- // NB Possibly should be asserting reset for PLLB, but there are timing
- // concerns here according to the docs
-
- value =
- BIT(SYS_CTRL_RST_COPRO ) |
- BIT(SYS_CTRL_RST_USBHS ) |
- BIT(SYS_CTRL_RST_USBHSPHYA ) |
- BIT(SYS_CTRL_RST_MACA ) |
- BIT(SYS_CTRL_RST_PCIEA ) |
- BIT(SYS_CTRL_RST_SGDMA ) |
- BIT(SYS_CTRL_RST_CIPHER ) |
- BIT(SYS_CTRL_RST_SATA ) |
- BIT(SYS_CTRL_RST_SATA_LINK ) |
- BIT(SYS_CTRL_RST_SATA_PHY ) |
- BIT(SYS_CTRL_RST_PCIEPHY ) |
- BIT(SYS_CTRL_RST_STATIC ) |
- BIT(SYS_CTRL_RST_UART1 ) |
- BIT(SYS_CTRL_RST_UART2 ) |
- BIT(SYS_CTRL_RST_MISC ) |
- BIT(SYS_CTRL_RST_I2S ) |
- BIT(SYS_CTRL_RST_SD ) |
- BIT(SYS_CTRL_RST_MACB ) |
- BIT(SYS_CTRL_RST_PCIEB ) |
- BIT(SYS_CTRL_RST_VIDEO ) |
- BIT(SYS_CTRL_RST_USBHSPHYB ) |
- BIT(SYS_CTRL_RST_USBDEV );
-
- writel(value, SYS_CTRL_RST_SET_CTRL);
-
- // Release reset to cores as per power on defaults
- writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);
-
- // Disable clocks to cores as per power-on defaults - must leave DDR
- // related clocks enabled otherwise we'll stop rather abruptly.
- value =
- BIT(SYS_CTRL_CLK_COPRO) |
- BIT(SYS_CTRL_CLK_DMA) |
- BIT(SYS_CTRL_CLK_CIPHER) |
- BIT(SYS_CTRL_CLK_SD) |
- BIT(SYS_CTRL_CLK_SATA) |
- BIT(SYS_CTRL_CLK_I2S) |
- BIT(SYS_CTRL_CLK_USBHS) |
- BIT(SYS_CTRL_CLK_MAC) |
- BIT(SYS_CTRL_CLK_PCIEA) |
- BIT(SYS_CTRL_CLK_STATIC) |
- BIT(SYS_CTRL_CLK_MACB) |
- BIT(SYS_CTRL_CLK_PCIEB) |
- BIT(SYS_CTRL_CLK_REF600) |
- BIT(SYS_CTRL_CLK_USBDEV);
-
- writel(value, SYS_CTRL_CLK_CLR_CTRL);
-
- // Enable clocks to cores as per power-on defaults
-
- // Set sys-control pin mux'ing as per power-on defaults
-
- writel(0, SYS_CONTROL_BASE + PINMUX_SECONDARY_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_TERTIARY_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_DEBUG_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_PULLUP_SEL);
-
- writel(0, SEC_CONTROL_BASE + PINMUX_SECONDARY_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_TERTIARY_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_DEBUG_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_PULLUP_SEL);
-
- // No need to save any state, as the ROM loader can determine whether reset
- // is due to power cycling or programatic action, just hit the (self-
- // clearing) CPU reset bit of the block reset register
- value =
- BIT(SYS_CTRL_RST_SCU) |
- BIT(SYS_CTRL_RST_ARM0) |
- BIT(SYS_CTRL_RST_ARM1);
-
- writel(value, SYS_CTRL_RST_SET_CTRL);
-}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- *
- * (C) Copyright 2002
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (1 << (CONFIG_TIMER_PRESCALE * 4)))
-#define TIMER_LOAD_VAL 0xFFFFFF
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER (TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR)) \
- / (TIMER_CLOCK / CONFIG_SYS_HZ)
-
-#define READ_TIMER_HW (TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR))
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int timer_init (void)
-{
- int32_t val;
-
- /* Start the counter ticking up */
- writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + TIMER_LOAD); /* reload value on overflow*/
-
- val = (CONFIG_TIMER_PRESCALE << TIMER_PRESCALE_SHIFT) |
- (TIMER_MODE_PERIODIC << TIMER_MODE_SHIFT) |
- (TIMER_ENABLE << TIMER_ENABLE_SHIFT); /* mask to enable timer*/
- writel(val, CONFIG_SYS_TIMERBASE + TIMER_CTRL); /* start timer */
-
- /* reset time */
- gd->arch.lastinc = READ_TIMER; /* capture current incrementer value */
- gd->arch.tbl = 0; /* start "advancing" time stamp */
-
- return(0);
-}
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
- return get_timer_masked () - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
- ulong tmo, tmp;
-
- if (usec > 100000) { /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
-
- tmp = get_timer (0); /* get current timestamp */
- while (get_timer (tmp) < tmo)/* loop till event */
- /*NOP*/;
- } else { /* else small number, convert to hw ticks */
- tmo = usec * (TIMER_CLOCK / 1000) / 1000;
- /* timeout is no more than 0.1s, and the hw timer will roll over at most once */
- tmp = READ_TIMER_HW;
- while (((READ_TIMER_HW -tmp) & TIMER_LOAD_VAL) < tmo)/* loop till event */
- /*NOP*/;
- }
-}
-
-ulong get_timer_masked (void)
-{
- ulong now = READ_TIMER; /* current tick value */
-
- if (now >= gd->arch.lastinc) { /* normal mode (non roll) */
- /* move stamp fordward with absoulte diff ticks */
- gd->arch.tbl += (now - gd->arch.lastinc);
- } else {
- /* we have rollover of incrementer */
- gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
- - gd->arch.lastinc) + now;
- }
- gd->arch.lastinc = now;
- return gd->arch.tbl;
-}
-
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- ulong tbclk;
- tbclk = CONFIG_SYS_HZ;
- return tbclk;
-}
+++ /dev/null
-#ifndef _NAS782X_CLOCK_H
-#define _NAS782X_CLOCK_H
-
-#include <asm/arch/sysctl.h>
-#include <asm/arch/cpu.h>
-
-/* bit numbers of clock control register */
-#define SYS_CTRL_CLK_COPRO 0
-#define SYS_CTRL_CLK_DMA 1
-#define SYS_CTRL_CLK_CIPHER 2
-#define SYS_CTRL_CLK_SD 3
-#define SYS_CTRL_CLK_SATA 4
-#define SYS_CTRL_CLK_I2S 5
-#define SYS_CTRL_CLK_USBHS 6
-#define SYS_CTRL_CLK_MACA 7
-#define SYS_CTRL_CLK_MAC SYS_CTRL_CLK_MACA
-#define SYS_CTRL_CLK_PCIEA 8
-#define SYS_CTRL_CLK_STATIC 9
-#define SYS_CTRL_CLK_MACB 10
-#define SYS_CTRL_CLK_PCIEB 11
-#define SYS_CTRL_CLK_REF600 12
-#define SYS_CTRL_CLK_USBDEV 13
-#define SYS_CTRL_CLK_DDR 14
-#define SYS_CTRL_CLK_DDRPHY 15
-#define SYS_CTRL_CLK_DDRCK 16
-
-/* bit numbers of reset control register */
-#define SYS_CTRL_RST_SCU 0
-#define SYS_CTRL_RST_COPRO 1
-#define SYS_CTRL_RST_ARM0 2
-#define SYS_CTRL_RST_ARM1 3
-#define SYS_CTRL_RST_USBHS 4
-#define SYS_CTRL_RST_USBHSPHYA 5
-#define SYS_CTRL_RST_MACA 6
-#define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA
-#define SYS_CTRL_RST_PCIEA 7
-#define SYS_CTRL_RST_SGDMA 8
-#define SYS_CTRL_RST_CIPHER 9
-#define SYS_CTRL_RST_DDR 10
-#define SYS_CTRL_RST_SATA 11
-#define SYS_CTRL_RST_SATA_LINK 12
-#define SYS_CTRL_RST_SATA_PHY 13
-#define SYS_CTRL_RST_PCIEPHY 14
-#define SYS_CTRL_RST_STATIC 15
-#define SYS_CTRL_RST_GPIO 16
-#define SYS_CTRL_RST_UART1 17
-#define SYS_CTRL_RST_UART2 18
-#define SYS_CTRL_RST_MISC 19
-#define SYS_CTRL_RST_I2S 20
-#define SYS_CTRL_RST_SD 21
-#define SYS_CTRL_RST_MACB 22
-#define SYS_CTRL_RST_PCIEB 23
-#define SYS_CTRL_RST_VIDEO 24
-#define SYS_CTRL_RST_DDR_PHY 25
-#define SYS_CTRL_RST_USBHSPHYB 26
-#define SYS_CTRL_RST_USBDEV 27
-#define SYS_CTRL_RST_ARMDBG 29
-#define SYS_CTRL_RST_PLLA 30
-#define SYS_CTRL_RST_PLLB 31
-
-static inline void reset_block(int block, int reset)
-{
- u32 reg;
- if (reset)
- reg = SYS_CTRL_RST_SET_CTRL;
- else
- reg = SYS_CTRL_RST_CLR_CTRL;
-
- writel(BIT(block), reg);
-}
-
-static inline void enable_clock(int block)
-{
- writel(BIT(block), SYS_CTRL_CLK_SET_CTRL);
-}
-
-static inline void disable_clock(int block)
-{
- writel(BIT(block), SYS_CTRL_CLK_CLR_CTRL);
-}
-
-int plla_set_config(int idx);
-
-#endif /* _NAS782X_CLOCK_H */
+++ /dev/null
-#ifndef _NAS782X_CPU_H
-#define _NAS782X_CPU_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#include <asm/io.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/timer.h>
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-
-#define BIT(x) (1 << (x))
-
-/* fix "implicit declaration of function" warnning */
-void *memalign(size_t alignment, size_t bytes);
-void free(void* mem);
-void *malloc(size_t bytes);
-void *calloc(size_t n, size_t elem_size);
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#endif /* _NAS782X_CPU_H */
+++ /dev/null
-#ifndef _NAS782X_HARDWARE_H
-#define _NAS782X_HARDWARE_H
-
-/* Core addresses */
-#define USB_HOST_BASE 0x40200000
-#define MACA_BASE 0x40400000
-#define MACB_BASE 0x40800000
-#define MAC_BASE MACA_BASE
-#define STATIC_CS0_BASE 0x41000000
-#define STATIC_CS1_BASE 0x41400000
-#define STATIC_CONTROL_BASE 0x41C00000
-#define SATA_DATA_BASE 0x42000000 /* non-functional, DMA just needs an address */
-#define GPIO_1_BASE 0x44000000
-#define GPIO_2_BASE 0x44100000
-#define UART_1_BASE 0x44200000
-#define UART_2_BASE 0x44300000
-#define SYS_CONTROL_BASE 0x44e00000
-#define SEC_CONTROL_BASE 0x44f00000
-#define RPSA_BASE 0x44400000
-#define RPSC_BASE 0x44500000
-#define DDR_BASE 0x44700000
-
-#define SATA_BASE 0x45900000
-#define SATA_0_REGS_BASE 0x45900000
-#define SATA_1_REGS_BASE 0x45910000
-#define SATA_DMA_REGS_BASE 0x459a0000
-#define SATA_SGDMA_REGS_BASE 0x459b0000
-#define SATA_HOST_REGS_BASE 0x459e0000
-
-#endif /* _NAS782X_HARDWARE_H */
+++ /dev/null
-#ifndef _NAS782X_PINMUX_H
-#define _NAS782X_PINMUX_H
-
-#include <asm/arch/cpu.h>
-
-#define PINMUX_GPIO 0
-#define PINMUX_2 1
-#define PINMUX_3 2
-#define PINMUX_4 3
-#define PINMUX_DEBUG 4
-#define PINMUX_ALT 5
-
-#define PINMUX_BANK_MFA 0
-#define PINMUX_BANK_MFB 1
-
-/* System control multi-function pin function selection */
-#define PINMUX_SECONDARY_SEL 0x14
-#define PINMUX_TERTIARY_SEL 0x8c
-#define PINMUX_QUATERNARY_SEL 0x94
-#define PINMUX_DEBUG_SEL 0x9c
-#define PINMUX_ALTERNATIVE_SEL 0xa4
-#define PINMUX_PULLUP_SEL 0xac
-
-#define PINMUX_UARTA_SIN PINMUX_ALT
-#define PINMUX_UARTA_SOUT PINMUX_ALT
-
-#define PINMUX_STATIC_DATA0 PINMUX_2
-#define PINMUX_STATIC_DATA1 PINMUX_2
-#define PINMUX_STATIC_DATA2 PINMUX_2
-#define PINMUX_STATIC_DATA3 PINMUX_2
-#define PINMUX_STATIC_DATA4 PINMUX_2
-#define PINMUX_STATIC_DATA5 PINMUX_2
-#define PINMUX_STATIC_DATA6 PINMUX_2
-#define PINMUX_STATIC_DATA7 PINMUX_2
-#define PINMUX_STATIC_NWE PINMUX_2
-#define PINMUX_STATIC_NOE PINMUX_2
-#define PINMUX_STATIC_NCS PINMUX_2
-#define PINMUX_STATIC_ADDR18 PINMUX_2
-#define PINMUX_STATIC_ADDR19 PINMUX_2
-
-#define PINMUX_MACA_MDC PINMUX_2
-#define PINMUX_MACA_MDIO PINMUX_2
-
-extern void pinmux_set(int bank, int pin, int func);
-
-#endif /* _NAS782X_PINMUX_H */
+++ /dev/null
-#ifndef _NAS782X_SPL_H
-#define _NAS782X_SPL_H
-
-#include <asm/arch/cpu.h>
-
-#endif /* _NAS782X_SPL_H */
+++ /dev/null
-#ifndef _NAS782X_SYSCTL_H
-#define _NAS782X_SYSCTL_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-#include <asm/arch/hardware.h>
-
-/**
- * System block reset and clock control
- */
-#define SYS_CTRL_PCI_STAT (SYS_CONTROL_BASE + 0x20)
-#define SYS_CTRL_CLK_SET_CTRL (SYS_CONTROL_BASE + 0x2C)
-#define SYS_CTRL_CLK_CLR_CTRL (SYS_CONTROL_BASE + 0x30)
-#define SYS_CTRL_RST_SET_CTRL (SYS_CONTROL_BASE + 0x34)
-#define SYS_CTRL_RST_CLR_CTRL (SYS_CONTROL_BASE + 0x38)
-#define SYS_CTRL_PLLSYS_CTRL (SYS_CONTROL_BASE + 0x48)
-#define SYS_CTRL_PLLSYS_KEY_CTRL (SYS_CONTROL_BASE + 0x6C)
-#define SYS_CTRL_GMAC_CTRL (SYS_CONTROL_BASE + 0x78)
-
-/* Scratch registers */
-#define SYS_CTRL_SCRATCHWORD0 (SYS_CONTROL_BASE + 0xc4)
-#define SYS_CTRL_SCRATCHWORD1 (SYS_CONTROL_BASE + 0xc8)
-#define SYS_CTRL_SCRATCHWORD2 (SYS_CONTROL_BASE + 0xcc)
-#define SYS_CTRL_SCRATCHWORD3 (SYS_CONTROL_BASE + 0xd0)
-
-#define SYS_CTRL_PLLA_CTRL0 (SYS_CONTROL_BASE + 0x1F0)
-#define SYS_CTRL_PLLA_CTRL1 (SYS_CONTROL_BASE + 0x1F4)
-#define SYS_CTRL_PLLA_CTRL2 (SYS_CONTROL_BASE + 0x1F8)
-#define SYS_CTRL_PLLA_CTRL3 (SYS_CONTROL_BASE + 0x1FC)
-
-#define SYS_CTRL_GMAC_AUTOSPEED 3
-#define SYS_CTRL_GMAC_RGMII 2
-#define SYS_CTRL_GMAC_SIMPLE_MUX 1
-#define SYS_CTRL_GMAC_CKEN_GTX 0
-
-#define SYS_CTRL_CKCTRL_CTRL_ADDR (SYS_CONTROL_BASE + 0x64)
-
-#define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0
-#define SYS_CTRL_CKCTRL_SLOW_BIT 8
-
-
-#define SYS_CTRL_USBHSMPH_CTRL (SYS_CONTROL_BASE + 0x40)
-#define SYS_CTRL_USBHSMPH_STAT (SYS_CONTROL_BASE + 0x44)
-#define SYS_CTRL_REF300_DIV (SYS_CONTROL_BASE + 0xF8)
-#define SYS_CTRL_USBHSPHY_CTRL (SYS_CONTROL_BASE + 0x84)
-#define SYS_CTRL_USB_CTRL (SYS_CONTROL_BASE + 0x90)
-
-/* System control multi-function pin function selection */
-#define SYS_CTRL_SECONDARY_SEL (SYS_CONTROL_BASE + 0x14)
-#define SYS_CTRL_TERTIARY_SEL (SYS_CONTROL_BASE + 0x8c)
-#define SYS_CTRL_QUATERNARY_SEL (SYS_CONTROL_BASE + 0x94)
-#define SYS_CTRL_DEBUG_SEL (SYS_CONTROL_BASE + 0x9c)
-#define SYS_CTRL_ALTERNATIVE_SEL (SYS_CONTROL_BASE + 0xa4)
-#define SYS_CTRL_PULLUP_SEL (SYS_CONTROL_BASE + 0xac)
-
-/* Secure control multi-function pin function selection */
-#define SEC_CTRL_SECONDARY_SEL (SEC_CONTROL_BASE + 0x14)
-#define SEC_CTRL_TERTIARY_SEL (SEC_CONTROL_BASE + 0x8c)
-#define SEC_CTRL_QUATERNARY_SEL (SEC_CONTROL_BASE + 0x94)
-#define SEC_CTRL_DEBUG_SEL (SEC_CONTROL_BASE + 0x9c)
-#define SEC_CTRL_ALTERNATIVE_SEL (SEC_CONTROL_BASE + 0xa4)
-#define SEC_CTRL_PULLUP_SEL (SEC_CONTROL_BASE + 0xac)
-
-#define SEC_CTRL_COPRO_CTRL (SEC_CONTROL_BASE + 0x68)
-#define SEC_CTRL_SECURE_CTRL (SEC_CONTROL_BASE + 0x98)
-#define SEC_CTRL_LEON_DEBUG (SEC_CONTROL_BASE + 0xF0)
-#define SEC_CTRL_PLLB_DIV_CTRL (SEC_CONTROL_BASE + 0xF8)
-#define SEC_CTRL_PLLB_CTRL0 (SEC_CONTROL_BASE + 0x1F0)
-#define SEC_CTRL_PLLB_CTRL1 (SEC_CONTROL_BASE + 0x1F4)
-#define SEC_CTRL_PLLB_CTRL8 (SEC_CONTROL_BASE + 0x1F4)
-
-#define REF300_DIV_INT_SHIFT 8
-#define REF300_DIV_FRAC_SHIFT 0
-#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
-#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
-
-#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16
-#define USBHSPHY_SUSPENDM_MANUAL_STATE 15
-#define USBHSPHY_ATE_ESET 14
-#define USBHSPHY_TEST_DIN 6
-#define USBHSPHY_TEST_ADD 2
-#define USBHSPHY_TEST_DOUT_SEL 1
-#define USBHSPHY_TEST_CLK 0
-
-#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5
-#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-
-#define USBAMUX_DEVICE BIT(4)
-
-#define USBPHY_REFCLKDIV_SHIFT 2
-#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT)
-
-#define USB_CTRL_USB_CKO_SEL_BIT 0
-
-#define USB_INT_CLK_XTAL 0
-#define USB_INT_CLK_REF300 2
-#define USB_INT_CLK_PLLB 3
-
-#define SYS_CTRL_GMAC_AUTOSPEED 3
-#define SYS_CTRL_GMAC_RGMII 2
-#define SYS_CTRL_GMAC_SIMPLE_MUX 1
-#define SYS_CTRL_GMAC_CKEN_GTX 0
-
-
-#define PLLB_ENSAT 3
-#define PLLB_OUTDIV 4
-#define PLLB_REFDIV 8
-#define PLLB_DIV_INT_SHIFT 8
-#define PLLB_DIV_FRAC_SHIFT 0
-#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
-#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#endif /* _NAS782X_SYSCTL_H */
+++ /dev/null
-#ifndef _NAS782X_TIMER_H
-#define _NAS782X_TIMER_H
-
-#define TIMER1_BASE (RPSA_BASE + 0x200)
-#define TIMER2_BASE (RPSA_BASE + 0x220)
-
-#define TIMER_LOAD 0
-#define TIMER_CURR 4
-#define TIMER_CTRL 8
-#define TIMER_INTR 0x0C
-
-#define TIMER_PRESCALE_SHIFT 2
-#define TIMER_PRESCALE_1 0
-#define TIMER_PRESCALE_16 1
-#define TIMER_PRESCALE_256 2
-#define TIMER_MODE_SHIFT 6
-#define TIMER_MODE_FREE_RUNNING 0
-#define TIMER_MODE_PERIODIC 1
-#define TIMER_ENABLE_SHIFT 7
-#define TIMER_DISABLE 0
-#define TIMER_ENABLE 1
-
-#endif /* _NAS782X_TIMER_H */
+++ /dev/null
-if TARGET_OX820
-
-config SYS_CPU
- default "arm1136"
-
-config SYS_SOC
- default "nas782x"
-
-config SYS_BOARD
- default "ox820"
-
-config SYS_CONFIG_NAME
- default "ox820"
-
-endif
+++ /dev/null
-SHEEVAPLUG BOARD
-S: Maintained
-F: board/ox820/
-F: include/configs/ox820.h
-F: configs/ox820_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += ox820.o
-obj-y += lowlevel_init.o
-
-obj-$(CONFIG_SPL_BUILD) += spl_start.o
-obj-$(CONFIG_SPL_BUILD) += ddr.o
-
+++ /dev/null
-/*******************************************************************
- *
- * File: ddr_oxsemi.c
- *
- * Description: Declarations for DDR routines and data objects
- *
- * Author: Julien Margetts
- *
- * Copyright: Oxford Semiconductor Ltd, 2009
- */
-#include <common.h>
-#include <asm/arch/clock.h>
-
-#include "ddr.h"
-
-typedef unsigned int UINT;
-
-// DDR TIMING PARAMETERS
-typedef struct {
- unsigned int holdoff_cmd_A;
- unsigned int holdoff_cmd_ARW;
- unsigned int holdoff_cmd_N;
- unsigned int holdoff_cmd_LM;
- unsigned int holdoff_cmd_R;
- unsigned int holdoff_cmd_W;
- unsigned int holdoff_cmd_PC;
- unsigned int holdoff_cmd_RF;
- unsigned int holdoff_bank_R;
- unsigned int holdoff_bank_W;
- unsigned int holdoff_dir_RW;
- unsigned int holdoff_dir_WR;
- unsigned int holdoff_FAW;
- unsigned int latency_CAS;
- unsigned int latency_WL;
- unsigned int recovery_WR;
- unsigned int width_update;
- unsigned int odt_offset;
- unsigned int odt_drive_all;
- unsigned int use_fixed_re;
- unsigned int delay_wr_to_re;
- unsigned int wr_slave_ratio;
- unsigned int rd_slave_ratio0;
- unsigned int rd_slave_ratio1;
-} T_DDR_TIMING_PARAMETERS;
-
-// DDR CONFIG PARAMETERS
-
-typedef struct {
- unsigned int ddr_mode;
- unsigned int width;
- unsigned int blocs;
- unsigned int banks8;
- unsigned int rams;
- unsigned int asize;
- unsigned int speed;
- unsigned int cmd_mode_wr_cl_bl;
-} T_DDR_CONFIG_PARAMETERS;
-
-//cmd_mode_wr_cl_bl
-//when SDR : cmd_mode_wr_cl_bl = 0x80200002 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
-//else cmd_mode_wr_cl_bl = 0x80200003 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
-
-// cmd_ bank_ dir_ lat_ rec_ width_ odt_ odt_ fix delay ratio
-// A F C update offset all re re_to_we w r0 r1
-// R L P R R W A A W W
-//Timing Parameters A W N M R W C F R W W R W S L R
-static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_1GB = { 4, 5, 0, 2, 4, 4,
- 5, 51, 23, 24, 9, 11, 18, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; //elida device.
-static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_2GB = { 4, 5, 0, 2, 4, 4,
- 5, 79, 22, 24, 9, 11, 20, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 };
-static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25_CL6_1GB = { 4, 5, 0, 2, 4, 4,
- 4, 51, 22, 26, 10, 12, 18, 6, 5, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; // 400MHz, Speedgrade 25 timings (1Gb parts)
-
-// D B B R A S
-// D W L K A S P
-//Config Parameters R D C 8 M Z D CMD_MODE
-//static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2,16, 1, 0, 1, 32,25,0x80200A53}; // 64 MByte
-static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2, 16, 1, 1, 1, 64,
- 25, 0x80200A53 }; // 128 MByte
-static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25_CL6 = { 2, 16, 1, 1, 1, 128,
- 25, 0x80200A63 }; // 256 MByte
-
-static void ddr_phy_poll_until_locked(void)
-{
- volatile UINT reg_tmp = 0;
- volatile UINT locked = 0;
-
- //Extra read to put in delay before starting to poll...
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
-
- //POLL C_DDR_PHY2_REG register until clock and flock
- //!!! Ideally have a timeout on this.
- while (locked == 0) {
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
-
- //locked when bits 30 and 31 are set
- if (reg_tmp & 0xC0000000) {
- locked = 1;
- }
- }
-}
-
-static void ddr_poll_until_not_busy(void)
-{
- volatile UINT reg_tmp = 0;
- volatile UINT busy = 1;
-
- //Extra read to put in delay before starting to poll...
- reg_tmp = *(volatile UINT *) C_DDR_STAT_REG; // read
-
- //POLL DDR_STAT register until no longer busy
- //!!! Ideally have a timeout on this.
- while (busy == 1) {
- reg_tmp = *(volatile UINT *) C_DDR_STAT_REG; // read
-
- //when bit 31 is clear - core is no longer busy
- if ((reg_tmp & 0x80000000) == 0x00000000) {
- busy = 0;
- }
- }
-}
-
-static void ddr_issue_command(int commmand)
-{
- *(volatile UINT *) C_DDR_CMD_REG = commmand;
- ddr_poll_until_not_busy();
-}
-
-static void ddr_timing_initialisation(
- const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters)
-{
- volatile UINT reg_tmp = 0;
- /* update the DDR controller registers for timing parameters */
- reg_tmp = (ddr_timing_parameters->holdoff_cmd_A << 0);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_ARW << 4);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_N << 8);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_LM << 12);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_R << 16);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_W << 20);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_PC << 24);
- *(volatile UINT *) C_DDR_REG_TIMING0 = reg_tmp;
-
- reg_tmp = (ddr_timing_parameters->holdoff_cmd_RF << 0);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_R << 8);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_W << 16);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_RW << 24);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_WR << 28);
- *(volatile UINT *) C_DDR_REG_TIMING1 = reg_tmp;
-
- reg_tmp = (ddr_timing_parameters->latency_CAS << 0);
- reg_tmp = reg_tmp + (ddr_timing_parameters->latency_WL << 4);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_FAW << 8);
- reg_tmp = reg_tmp + (ddr_timing_parameters->width_update << 16);
- reg_tmp = reg_tmp + (ddr_timing_parameters->odt_offset << 21);
- reg_tmp = reg_tmp + (ddr_timing_parameters->odt_drive_all << 24);
-
- *(volatile UINT *) C_DDR_REG_TIMING2 = reg_tmp;
-
- /* Program the timing parameters in the PHY too */
- reg_tmp = (ddr_timing_parameters->use_fixed_re << 16)
- | (ddr_timing_parameters->delay_wr_to_re << 8)
- | (ddr_timing_parameters->latency_WL << 4)
- | (ddr_timing_parameters->latency_CAS << 0);
-
- *(volatile UINT *) C_DDR_REG_PHY_TIMING = reg_tmp;
-
- reg_tmp = ddr_timing_parameters->wr_slave_ratio;
-
- *(volatile UINT *) C_DDR_REG_PHY_WR_RATIO = reg_tmp;
-
- reg_tmp = ddr_timing_parameters->rd_slave_ratio0;
- reg_tmp += ddr_timing_parameters->rd_slave_ratio1 << 8;
-
- *(volatile UINT *) C_DDR_REG_PHY_RD_RATIO = reg_tmp;
-
-}
-
-static void ddr_normal_initialisation(
- const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters, int mhz)
-{
- int i;
- volatile UINT tmp = 0;
- volatile UINT reg_tmp = 0;
- volatile UINT emr_cmd = 0;
- UINT refresh;
-
- //Total size of memory in Mbits...
- tmp = ddr_config_parameters->rams * ddr_config_parameters->asize
- * ddr_config_parameters->width;
- //Deduce value to program into DDR_CFG register...
- switch (tmp) {
- case 16:
- reg_tmp = 0x00020000 * 1;
- break;
- case 32:
- reg_tmp = 0x00020000 * 2;
- break;
- case 64:
- reg_tmp = 0x00020000 * 3;
- break;
- case 128:
- reg_tmp = 0x00020000 * 4;
- break;
- case 256:
- reg_tmp = 0x00020000 * 5;
- break;
- case 512:
- reg_tmp = 0x00020000 * 6;
- break;
- case 1024:
- reg_tmp = 0x00020000 * 7;
- break;
- case 2048:
- reg_tmp = 0x00020000 * 8;
- break;
- default:
- reg_tmp = 0; //forces sims not to work if badly configured
- }
-
- //Memory width
- tmp = ddr_config_parameters->rams * ddr_config_parameters->width;
- switch (tmp) {
- case 8:
- reg_tmp = reg_tmp + 0x00400000;
- break;
- case 16:
- reg_tmp = reg_tmp + 0x00200000;
- break;
- case 32:
- reg_tmp = reg_tmp + 0x00000000;
- break;
- default:
- reg_tmp = 0; //forces sims not to work if badly configured
- }
-
- //Setup DDR Mode
- switch (ddr_config_parameters->ddr_mode) {
- case 0:
- reg_tmp = reg_tmp + 0x00000000;
- break; //SDR
- case 1:
- reg_tmp = reg_tmp + 0x40000000;
- break; //DDR
- case 2:
- reg_tmp = reg_tmp + 0x80000000;
- break; //DDR2
- default:
- reg_tmp = 0; //forces sims not to work if badly configured
- }
-
- //Setup Banks
- if (ddr_config_parameters->banks8 == 1) {
- reg_tmp = reg_tmp + 0x00800000;
- }
-
- //Program DDR_CFG register...
- *(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
-
- //Configure PHY0 reg - se_mode is bit 1,
- //needs to be 1 for DDR (single_ended drive)
- switch (ddr_config_parameters->ddr_mode) {
- case 0:
- reg_tmp = 2 + (0 << 4);
- break; //SDR
- case 1:
- reg_tmp = 2 + (4 << 4);
- break; //DDR
- case 2:
- reg_tmp = 0 + (4 << 4);
- break; //DDR2
- default:
- reg_tmp = 0;
- }
-
- //Program DDR_PHY0 register...
- *(volatile UINT *) C_DDR_REG_PHY0 = reg_tmp;
-
- //Read DDR_PHY* registers to exercise paths for vcd
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY3;
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY1;
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY0;
-
- //Start up sequences - Different dependant on DDR mode
- switch (ddr_config_parameters->ddr_mode) {
- case 2: //DDR2
- //Start-up sequence: follows procedure described in Micron datasheet.
- //start up DDR PHY DLL
- reg_tmp = 0x00022828; // dll on, start point and inc = h28
- *(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
-
- reg_tmp = 0x00032828; // start on, dll on, start point and inc = h28
- *(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
-
- ddr_phy_poll_until_locked();
-
- udelay(200); //200us
-
- //Startup SDRAM...
- //!!! Software: CK should be running for 200us before wake-up
- ddr_issue_command( C_CMD_WAKE_UP);
- ddr_issue_command( C_CMD_NOP);
- ddr_issue_command( C_CMD_PRECHARGE_ALL);
- ddr_issue_command( C_CMD_DDR2_EMR2);
- ddr_issue_command( C_CMD_DDR2_EMR3);
-
- emr_cmd = C_CMD_DDR2_EMR1 + C_CMD_ODT_75 + C_CMD_REDUCED_DRIVE
- + C_CMD_ENABLE_DLL;
-
- ddr_issue_command(emr_cmd);
- //Sets CL=3; BL=8 but also reset DLL to trigger a DLL initialisation...
- udelay(1); //1us
- ddr_issue_command(
- ddr_config_parameters->cmd_mode_wr_cl_bl
- + C_CMD_RESET_DLL);
- udelay(1); //1us
-
- //!!! Software: Wait 200 CK cycles before...
- //for(i=1; i<=2; i++) {
- ddr_issue_command(C_CMD_PRECHARGE_ALL);
- // !!! Software: Wait here at least 8 CK cycles
- //}
- //need a wait here to ensure PHY DLL lock before the refresh is issued
- udelay(1); //1us
- for (i = 1; i <= 2; i++) {
- ddr_issue_command( C_CMD_AUTO_REFRESH);
- //!!! Software: Wait here at least 8 CK cycles to satify tRFC
- udelay(1); //1us
- }
- //As before but without 'RESET_DLL' bit set...
- ddr_issue_command(ddr_config_parameters->cmd_mode_wr_cl_bl);
- udelay(1); //1us
- // OCD commands
- ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_DFLT);
- ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_EXIT);
- break;
-
- default:
- break; //Do nothing
- }
-
- //Enable auto-refresh
-
- // 8192 Refreshes required every 64ms, so maximum refresh period is 7.8125 us
- // We have a 400 MHz DDR clock (2.5ns period) so max period is 3125 cycles
- // Our core now does 8 refreshes in a go, so we multiply this period by 8
-
- refresh = (64000 * mhz) / 8192; // Refresh period in clocks
-
- reg_tmp = *(volatile UINT *) C_DDR_CFG_REG; // read
-#ifdef BURST_REFRESH_ENABLE
- reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 8);
- reg_tmp |= C_CFG_BURST_REFRESH_ENABLE;
-#else
- reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 1);
- reg_tmp &= ~C_CFG_BURST_REFRESH_ENABLE;
-#endif
- *(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
-
- //Verify register contents
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
- //printf("Warning XXXXXXXXXXXXXXXXXXXXXX - get bad read data from C_DDR_PHY2_REG, though it looks OK on bus XXXXXXXXXXXXXXXXXX");
- //TBD Check_data (read_data, dll_reg, "Error: bad C_DDR_PHY2_REG read", tb_pass);
- reg_tmp = *(volatile UINT *) C_DDR_CFG_REG; // read
- //TBD Check_data (read_data, cfg_reg, "Error: bad DDR_CFG read", tb_pass);
-
- //disable optimised wrapping
- if (ddr_config_parameters->ddr_mode == 2) {
- reg_tmp = 0xFFFF0000;
- *(volatile UINT *) C_DDR_REG_IGNORE = reg_tmp;
- }
-
- //enable midbuffer followon
- reg_tmp = *(volatile UINT *) C_DDR_ARB_REG; // read
- reg_tmp = 0xFFFF0000 | reg_tmp;
- *(volatile UINT *) C_DDR_ARB_REG = reg_tmp;
-
- // Enable write behind coherency checking for all clients
-
- reg_tmp = 0xFFFF0000;
- *(volatile UINT *) C_DDR_AHB4_REG = reg_tmp;
-
- //Wait for 200 clock cycles for SDRAM DLL to lock...
- udelay(1); //1us
-}
-
-// Function used to Setup DDR core
-
-void ddr_setup(int mhz)
-{
- static const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters =
- &C_TP_DDR2_25_CL6_1GB;
- static const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters =
- &C_CP_DDR2_25_CL6;
-
- //Bring core out of Reset
- *(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON;
-
- //DDR TIMING INITIALISTION
- ddr_timing_initialisation(ddr_timing_parameters);
-
- //DDR NORMAL INITIALISATION
- ddr_normal_initialisation(ddr_config_parameters, mhz);
-
- // route all writes through one client
- *(volatile UINT *) C_DDR_TRANSACTION_ROUTING = (0
- << DDR_ROUTE_CPU0_INSTR_SHIFT)
- | (1 << DDR_ROUTE_CPU0_RDDATA_SHIFT)
- | (3 << DDR_ROUTE_CPU0_WRDATA_SHIFT)
- | (2 << DDR_ROUTE_CPU1_INSTR_SHIFT)
- | (3 << DDR_ROUTE_CPU1_RDDATA_SHIFT)
- | (3 << DDR_ROUTE_CPU1_WRDATA_SHIFT);
-
- //Bring all clients out of reset
- *(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON + 0x0000FFFF;
-
-}
-
-void set_ddr_timing(unsigned int w, unsigned int i)
-{
- unsigned int reg;
- unsigned int wnow = 16;
- unsigned int inow = 32;
-
- /* reset all timing controls to known value (31) */
- writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST | DDR_PHY_TIMING_CK,
- DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
-
- /* step up or down read delay to the requested value */
- while (wnow != w) {
- if (wnow < w) {
- reg = DDR_PHY_TIMING_INC;
- wnow++;
- } else {
- reg = 0;
- wnow--;
- }
- writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_W_CE | reg,
- DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
- }
-
- /* now write delay */
- while (inow != i) {
- if (inow < i) {
- reg = DDR_PHY_TIMING_INC;
- inow++;
- } else {
- reg = 0;
- inow--;
- }
- writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_I_CE | reg,
- DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
- }
-}
-
-//Function used to Setup SDRAM in DDR/SDR mode
-void init_ddr(int mhz)
-{
- /* start clocks */
- enable_clock(SYS_CTRL_CLK_DDRPHY);
- enable_clock(SYS_CTRL_CLK_DDR);
- enable_clock(SYS_CTRL_CLK_DDRCK);
-
- /* bring phy and core out of reset */
- reset_block(SYS_CTRL_RST_DDR_PHY, 0);
- reset_block(SYS_CTRL_RST_DDR, 0);
-
- /* DDR runs at half the speed of the CPU */
- ddr_setup(mhz >> 1);
- return;
-}
+++ /dev/null
-/*******************************************************************
-*
-* File: ddr_oxsemi.h
-*
-* Description: Declarations for DDR routines and data objects
-*
-* Author: Julien Margetts
-*
-* Copyright: Oxford Semiconductor Ltd, 2009
-*/
-
-void ddr_oxsemi_setup(int mhz);
-
-/* define to refresh in bursts of 8 */
-#define BURST_REFRESH_ENABLE
-
-#define DDR_BASE 0x44700000
-
-#define C_DDR_CFG_REG (DDR_BASE + 0x00)
-#define C_CFG_DDR 0x80000000
-#define C_CFG_SDR 0x00000000
-#define C_CFG_WIDTH8 0x00200000
-#define C_CFG_WIDTH16 0x00100000
-#define C_CFG_WIDTH32 0x00000000
-#define C_CFG_SIZE_FACTOR 0x00020000
-#define C_CFG_REFRESH_ENABLE 0x00010000
-#define C_CFG_BURST_REFRESH_ENABLE 0x01000000
-#define C_CFG_SIZE(x) (x << 17)
-#define CFG_SIZE_2MB 1
-#define CFG_SIZE_4MB 2
-#define CFG_SIZE_8MB 3
-#define CFG_SIZE_16MB 4
-#define CFG_SIZE_32MB 5
-#define CFG_SIZE_64MB 6
-#define CFG_SIZE_128MB 7
-
-#define C_DDR_BLKEN_REG (DDR_BASE + 0x04)
-#define C_BLKEN_DDR_ON 0x80000000
-
-#define C_DDR_STAT_REG (DDR_BASE + 0x08)
-
-#define C_DDR_CMD_REG (DDR_BASE + 0x0C)
-#define C_CMD_SEND_COMMAND (1UL << 31) | (1 << 21) // RAS/CAS/WE/CS all low(active), CKE High, indicates
-#define C_CMD_WAKE_UP 0x80FC0000 // Asserts CKE
-#define C_CMD_MODE_SDR 0x80200022 // Sets CL=2 BL=4
-#define C_CMD_MODE_DDR 0x80200063 // Sets CL=2.5 BL=8
-#define C_CMD_RESET_DLL 0x00000100 // A8=1 Use in conjunction with C_CMD_MODE_DDR
-#define C_CMD_PRECHARGE_ALL 0x80280400
-#define C_CMD_AUTO_REFRESH 0x80240000
-#define C_CMD_SELF_REFRESH 0x80040000 // As AUTO-REFRESH but with CKE low
-#define C_CMD_NOP 0x803C0000 // NOP just to insert guaranteed delay
-#define C_CMD_DDR2_EMR1 0x80210000 // Load extended mode register 1 with zeros (for init), CKE still set
-//#define C_CMD_DDR2_EMR1 0x80210400 // Load extended mode register 1 with zeros (for init), CKE still set
-#define C_CMD_ENABLE_DLL 0x00000000 // Values used in conjuction with C_CMD_DDR2_EMR1
-#define C_CMD_DISABLE_DLL 0x00000001
-#define C_CMD_REDUCED_DRIVE 0x00000002
-#define C_CMD_ODT_DISABLED 0x00000000
-#define C_CMD_ODT_50 0x00000044
-#define C_CMD_ODT_75 0x00000004
-#define C_CMD_ODT_150 0x00000040
-#define C_CMD_MODE_DDR2_OCD_DFLT 0x00000380
-#define C_CMD_MODE_DDR2_OCD_EXIT 0x00000000
-
-#define C_CMD_DDR2_EMR2 0x80220000 // Load extended mode register 2 with zeros (for init), CKE still set
-#define C_CMD_DDR2_EMR3 0x80230000 // Load extended mode register 3 with zeros (for init), CKE still set
-
-#define C_DDR_AHB_REG (DDR_BASE + 0x10)
-#define C_AHB_NO_RCACHES 0xFFFF0000
-#define C_AHB_FLUSH_ALL_RCACHES 0x0000FFFF
-#define C_AHB_FLUSH_AHB0_RCACHE 0x00000001
-#define C_AHB_FLUSH_AHB1_RCACHE 0x00000002
-
-#define C_DDR_DLL_REG (DDR_BASE + 0x14)
-#define C_DLL_DISABLED 0x00000000
-#define C_DLL_MANUAL 0x80000000
-#define C_DLL_AUTO_OFFSET 0xA0000000
-#define C_DLL_AUTO_IN_REFRESH 0xC0000000
-#define C_DLL_AUTOMATIC 0xE0000000
-
-#define C_DDR_MON_REG (DDR_BASE + 0x18)
-#define C_MON_ALL 0x00000010
-#define C_MON_CLIENT 0x00000000
-
-#define C_DDR_DIAG_REG (DDR_BASE + 0x1C)
-#define C_DDR_DIAG2_REG (DDR_BASE + 0x20)
-
-#define C_DDR_IOC_REG (DDR_BASE + 0x24)
-#define C_DDR_IOC_PWR_DWN (1 << 10)
-#define C_DDR_IOC_SEL_SSTL (1 << 9)
-#define C_DDR_IOC_CK_DRIVE(x) ((x) << 6)
-#define C_DDR_IOC_DQ_DRIVE(x) ((x) << 3)
-#define C_DDR_IOC_XX_DRIVE(x) ((x) << 0)
-
-#define C_DDR_ARB_REG (DDR_BASE + 0x28)
-#define C_DDR_ARB_MIDBUF (1 << 4)
-#define C_DDR_ARB_LRUBANK (1 << 3)
-#define C_DDR_ARB_REQAGE (1 << 2)
-#define C_DDR_ARB_DATDIR (1 << 1)
-#define C_DDR_ARB_DATDIR_NC (1 << 0)
-
-#define C_TOP_ADDRESS_BIT_TEST 22
-#define C_MEM_BASE C_SDRAM_BASE
-
-#define C_MEM_TEST_BASE 0
-#define C_MEM_TEST_LEN 1920
-#define C_MAX_RAND_ACCESS_LEN 16
-
-#define C_DDR_REG_IGNORE (DDR_BASE + 0x2C)
-#define C_DDR_AHB4_REG (DDR_BASE + 0x44)
-
-#define C_DDR_REG_TIMING0 (DDR_BASE + 0x34)
-#define C_DDR_REG_TIMING1 (DDR_BASE + 0x38)
-#define C_DDR_REG_TIMING2 (DDR_BASE + 0x3C)
-
-#define C_DDR_REG_PHY0 (DDR_BASE + 0x48)
-#define C_DDR_REG_PHY1 (DDR_BASE + 0x4C)
-#define C_DDR_REG_PHY2 (DDR_BASE + 0x50)
-#define C_DDR_REG_PHY3 (DDR_BASE + 0x54)
-
-#define C_DDR_REG_GENERIC (DDR_BASE + 0x60)
-
-#define C_OXSEMI_DDRC_SIGNATURE 0x054415AA
-
-#define DDR_PHY_BASE (DDR_BASE + 0x80000)
-#define DDR_PHY_TIMING (DDR_PHY_BASE + 0x48)
-#define DDR_PHY_TIMING_CK (1 << 12)
-#define DDR_PHY_TIMING_INC (1 << 13)
-#define DDR_PHY_TIMING_W_CE (1 << 14)
-#define DDR_PHY_TIMING_W_RST (1 << 15)
-#define DDR_PHY_TIMING_I_CE (1 << 16)
-#define DDR_PHY_TIMING_I_RST (1 << 17)
-
-#define C_DDR_REG_PHY_TIMING (DDR_PHY_BASE + 0x50)
-#define C_DDR_REG_PHY_WR_RATIO (DDR_PHY_BASE + 0x74)
-#define C_DDR_REG_PHY_RD_RATIO (DDR_PHY_BASE + 0x78)
-
-#define C_DDR_TRANSACTION_ROUTING (DDR_PHY_BASE + 0xC8)
-#define DDR_ROUTE_CPU0_INSTR_SHIFT 0
-#define DDR_ROUTE_CPU0_RDDATA_SHIFT 4
-#define DDR_ROUTE_CPU0_WRDATA_SHIFT 6
-#define DDR_ROUTE_CPU1_INSTR_SHIFT 8
-#define DDR_ROUTE_CPU1_RDDATA_SHIFT 12
-#define DDR_ROUTE_CPU1_WRDATA_SHIFT 14
-
-unsigned int ddrc_signature(void);
-void set_ddr_timing(unsigned int w, unsigned int i);
-int pause(unsigned int us);
-void set_ddr_sel(int val);
+++ /dev/null
-#include <config.h>
-#ifndef CONFIG_SPL_BUILD
-
-.globl lowlevel_init
-lowlevel_init:
- /*
- * Copy exception table to relocated address in internal SRAM
- */
- ldr r0, src /* Address of exception table in flash */
- ldr r1, dest /* Relocated address of exception table */
- ldmia r0!, {r3-r10} /* Copy exception table and jump values from */
- stmia r1!, {r3-r10} /* FLASH to relocated address */
- ldmia r0!, {r3-r10}
- stmia r1!, {r3-r10}
- mov pc, lr
-
-src: .word CONFIG_SYS_TEXT_BASE
-dest: .word CONFIG_SRAM_BASE
-
-#endif
\ No newline at end of file
+++ /dev/null
-#include <common.h>
-#include <spl.h>
-#include <phy.h>
-#include <netdev.h>
-#include <ide.h>
-#include <nand.h>
-#include <asm/arch/spl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sysctl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SPL_BUILD
-
-#ifdef DEBUG
-#define DILIGENCE (1048576/4)
-static int test_memory(u32 memory)
-{
- volatile u32 *read;
- volatile u32 *write;
- const u32 INIT_PATTERN = 0xAA55AA55;
- const u32 INC_PATTERN = 0x01030507;
- u32 pattern;
- int check;
- int i;
-
- check = 0;
- read = write = (volatile u32 *) memory;
- pattern = INIT_PATTERN;
- for (i = 0; i < DILIGENCE; i++) {
- *write++ = pattern;
- pattern += INC_PATTERN;
- }
- puts("testing\n");
- pattern = INIT_PATTERN;
- for (i = 0; i < DILIGENCE; i++) {
- check += (pattern == *read++) ? 1 : 0;
- pattern += INC_PATTERN;
- }
- return (check == DILIGENCE) ? 0 : -1;
-}
-#endif
-
-void uart_init(void)
-{
- /* Reset UART1 */
- reset_block(SYS_CTRL_RST_UART1, 1);
- udelay(100);
- reset_block(SYS_CTRL_RST_UART1, 0);
- udelay(100);
-
- /* Setup pin mux'ing for UART1 */
- pinmux_set(PINMUX_BANK_MFA, 30, PINMUX_UARTA_SIN);
- pinmux_set(PINMUX_BANK_MFA, 31, PINMUX_UARTA_SOUT);
-}
-
-extern void init_ddr(int mhz);
-
-void board_inithw(void)
-{
- int plla_freq;
-#ifdef DEBUG
- int i;
-#endif /* DEBUG */
-
- timer_init();
- uart_init();
- preloader_console_init();
-
- plla_freq = plla_set_config(CONFIG_PLLA_FREQ_MHZ);
- init_ddr(plla_freq);
-
-#ifdef DEBUG
- if(test_memory(CONFIG_SYS_SDRAM_BASE)) {
- puts("memory test failed\n");
- } else {
- puts("memory test done\n");
- }
-#endif /* DEBUG */
-#ifdef CONFIG_SPL_BSS_DRAM_START
- extern char __bss_dram_start[];
- extern char __bss_dram_end[];
- memset(&__bss_dram_start, 0, __bss_dram_end - __bss_dram_start);
-#endif
-}
-
-void board_init_f(ulong dummy)
-{
- /* Set the stack pointer. */
- asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* Set global data pointer. */
- gd = &gdata;
-
- board_inithw();
-
- board_init_r(NULL, 0);
-}
-
-u32 spl_boot_device(void)
-{
- return CONFIG_SPL_BOOT_DEVICE;
-}
-
-#ifdef CONFIG_SPL_BLOCK_SUPPORT
-void spl_block_device_init(void)
-{
- ide_init();
-}
-#endif
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- return (serial_tstc() && serial_getc() == 'c');
-}
-#endif
-
-void spl_display_print(void)
-{
- /* print a hint, so that we will not use the wrong SPL by mistake */
- puts(" Boot device: " BOOT_DEVICE_TYPE "\n" );
-}
-
-void lowlevel_init(void)
-{
-}
-
-#ifdef USE_DL_PREFIX
-/* quick and dirty memory allocation */
-static ulong next_mem = CONFIG_SPL_MALLOC_START;
-
-void *memalign(size_t alignment, size_t bytes)
-{
- ulong mem = ALIGN(next_mem, alignment);
-
- next_mem = mem + bytes;
-
- if (next_mem > CONFIG_SYS_SDRAM_BASE + CONFIG_MIN_SDRAM_SIZE) {
- printf("spl: out of memory\n");
- hang();
- }
-
- return (void *)mem;
-}
-
-void free(void* mem)
-{
-}
-#endif
-
-#endif /* CONFIG_SPL_BUILD */
-
-int board_early_init_f(void)
-{
- return 0;
-}
-
-#define STATIC_CTL_BANK0 (STATIC_CONTROL_BASE + 4)
-#define STATIC_READ_CYCLE_SHIFT 0
-#define STATIC_DELAYED_OE (1 << 7)
-#define STATIC_WRITE_CYCLE_SHIFT 8
-#define STATIC_WRITE_PULSE_SHIFT 16
-#define STATIC_WRITE_BURST_EN (1 << 23)
-#define STATIC_TURN_AROUND_SHIFT 24
-#define STATIC_BUFFER_PRESENT (1 << 28)
-#define STATIC_READ_BURST_EN (1 << 29)
-#define STATIC_BUS_WIDTH8 (0 << 30)
-#define STATIC_BUS_WIDTH16 (1 << 30)
-#define STATIC_BUS_WIDTH32 (2 << 30)
-
-void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
- unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- nandaddr &= ~(BIT(NAND_ALE_ADDR_PIN) | BIT(NAND_CLE_ADDR_PIN));
- if (ctrl & NAND_CLE)
- nandaddr |= BIT(NAND_CLE_ADDR_PIN);
- else if (ctrl & NAND_ALE)
- nandaddr |= BIT(NAND_ALE_ADDR_PIN);
- this->IO_ADDR_W = (void __iomem *) nandaddr;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, (void __iomem *) nandaddr);
-}
-
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOOT_FROM_NAND)
-
-int nand_dev_ready(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd->priv;
-
- udelay(chip->chip_delay);
-
- return 1;
-}
-
-void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- int i;
- struct nand_chip *chip = mtd->priv;
-
- for (i = 0; i < len; i++)
- buf[i] = readb(chip->IO_ADDR_R);
-}
-
-void nand_dev_reset(struct nand_chip *chip)
-{
- writeb(NAND_CMD_RESET, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
- udelay(chip->chip_delay);
- writeb(NAND_CMD_STATUS, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
- while (!(readb(chip->IO_ADDR_R) & NAND_STATUS_READY)) {
- ;
- }
-}
-
-#else
-
-#define nand_dev_reset(chip) /* framework will reset the chip anyway */
-#define nand_read_buf NULL /* framework will provide a default one */
-#define nand_dev_ready NULL /* dev_ready is optional */
-
-#endif
-
-int board_nand_init(struct nand_chip *chip)
-{
- /* Block reset Static core */
- reset_block(SYS_CTRL_RST_STATIC, 1);
- reset_block(SYS_CTRL_RST_STATIC, 0);
-
- /* Enable clock to Static core */
- enable_clock(SYS_CTRL_CLK_STATIC);
-
- /* enable flash support on static bus.
- * Enable static bus onto GPIOs, only CS0 */
- pinmux_set(PINMUX_BANK_MFA, 12, PINMUX_STATIC_DATA0);
- pinmux_set(PINMUX_BANK_MFA, 13, PINMUX_STATIC_DATA1);
- pinmux_set(PINMUX_BANK_MFA, 14, PINMUX_STATIC_DATA2);
- pinmux_set(PINMUX_BANK_MFA, 15, PINMUX_STATIC_DATA3);
- pinmux_set(PINMUX_BANK_MFA, 16, PINMUX_STATIC_DATA4);
- pinmux_set(PINMUX_BANK_MFA, 17, PINMUX_STATIC_DATA5);
- pinmux_set(PINMUX_BANK_MFA, 18, PINMUX_STATIC_DATA6);
- pinmux_set(PINMUX_BANK_MFA, 19, PINMUX_STATIC_DATA7);
-
- pinmux_set(PINMUX_BANK_MFA, 20, PINMUX_STATIC_NWE);
- pinmux_set(PINMUX_BANK_MFA, 21, PINMUX_STATIC_NOE);
- pinmux_set(PINMUX_BANK_MFA, 22, PINMUX_STATIC_NCS);
- pinmux_set(PINMUX_BANK_MFA, 23, PINMUX_STATIC_ADDR18);
- pinmux_set(PINMUX_BANK_MFA, 24, PINMUX_STATIC_ADDR19);
-
- /* Setup the static bus CS0 to access FLASH */
-
- writel((0x3f << STATIC_READ_CYCLE_SHIFT)
- | (0x3f << STATIC_WRITE_CYCLE_SHIFT)
- | (0x1f << STATIC_WRITE_PULSE_SHIFT)
- | (0x03 << STATIC_TURN_AROUND_SHIFT) |
- STATIC_BUS_WIDTH16,
- STATIC_CTL_BANK0);
-
- chip->cmd_ctrl = nand_hwcontrol;
- chip->ecc.mode = NAND_ECC_SOFT;
- chip->chip_delay = 30;
- chip->dev_ready = nand_dev_ready;
- chip->read_buf = nand_read_buf;
-
- nand_dev_reset(chip);
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- gd->bd->bi_arch_number = MACH_TYPE_OXNAS;
-
- /* assume uart is already initialized by SPL */
-
-#if defined(CONFIG_START_IDE)
- puts("IDE: ");
- ide_init();
-#endif
-
- return 0;
-}
-
-/* copied from board/evb64260/sdram_init.c */
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-static long int dram_size (long int *base, long int maxsize)
-{
- volatile long int *addr, *b = base;
- long int cnt, val, save1, save2;
-
-#define STARTVAL (CONFIG_MIN_SDRAM_SIZE / 2) /* start test at half size */
- for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
- cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save1 = *addr; /* save contents of addr */
- save2 = *b; /* save contents of base */
-
- *addr = cnt; /* write cnt to addr */
- *b = 0; /* put null at base */
-
- /* check at base address */
- if ((*b) != 0) {
- *addr = save1; /* restore *addr */
- *b = save2; /* restore *b */
- return (0);
- }
- val = *addr; /* read *addr */
-
- *addr = save1;
- *b = save2;
-
- if (val != cnt) {
- /* fix boundary condition.. STARTVAL means zero */
- if (cnt == STARTVAL / sizeof (long))
- cnt = 0;
- return (cnt * sizeof (long));
- }
- }
- return maxsize;
-}
-
-int dram_init(void)
-{
- gd->ram_size = dram_size((long int *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_MAX_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- u32 value;
-
- /* set the pin multiplexers to enable talking to Ethernent Phys */
- pinmux_set(PINMUX_BANK_MFA, 3, PINMUX_MACA_MDC);
- pinmux_set(PINMUX_BANK_MFA, 4, PINMUX_MACA_MDIO);
-
- // Ensure the MAC block is properly reset
- reset_block(SYS_CTRL_RST_MAC, 1);
- udelay(10);
- reset_block(SYS_CTRL_RST_MAC, 0);
-
- // Enable the clock to the MAC block
- enable_clock(SYS_CTRL_CLK_MAC);
-
- value = readl(SYS_CTRL_GMAC_CTRL);
- /* Use simple mux for 25/125 Mhz clock switching */
- value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX);
- /* Enable GMII_GTXCLK to follow GMII_REFCLK - required for gigabit PHY */
- value |= BIT(SYS_CTRL_GMAC_CKEN_GTX);
- /* set auto tx speed */
- value |= BIT(SYS_CTRL_GMAC_AUTOSPEED);
-
- writel(value, SYS_CTRL_GMAC_CTRL);
-
- return designware_initialize(MAC_BASE, PHY_INTERFACE_MODE_RGMII);
-}
-
+++ /dev/null
-.section .init
-.globl _spl_start
-_spl_start:
- b _start
- b _start+0x4
- b _start+0x8
- b _start+0xc
- b _start+0x10
- b _start+0x14
- b _start+0x18
- b _start+0x1c
- .space 0x30 - (. - _spl_start)
- .ascii "BOOT" /* 0x30 signature*/
- .word 0x50 /* 0x34 header size itself */
- .word 0 /* 0x38 */
- .word 0x5000f000 /* boot report location */
- .word _start /* 0x40 */
-
-main_crc_size: .word code_size /* 0x44 filled by linker */
-main_crc: .word 0 /* 0x48 fill later */
-header_crc: .word 0 /* 0x4C header crc*/
+++ /dev/null
-/*
- * on behalf of DENX Software Engineering GmbH
- *
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-MEMORY
-{
- sram (rwx) : ORIGIN = CONFIG_SPL_TEXT_BASE, LENGTH = CONFIG_SPL_MAX_SIZE
- dram : ORIGIN = CONFIG_SPL_BSS_DRAM_START, LENGTH = CONFIG_SPL_BSS_DRAM_SIZE
-}
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_spl_start)
-SECTIONS
-{
- .text.0 :
- {
- *(.init*)
- }
-
-
- /* Start of the rest of the SPL */
- code_start = . ;
-
- .text.1 :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- __image_copy_end = .;
- code_size = . - code_start;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- . = ALIGN(0x800);
-
- _end = .;
-
- .bss.sram __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss.stdio_devices)
- *(.bss.serial_current)
- . = ALIGN(4);
- __bss_end = .;
- }
-
- .bss : {
- __bss_dram_start = .;
- *(.bss*)
- __bss_dram_end = .;
- } > dram
-
- /DISCARD/ : { *(.bss*) }
- /DISCARD/ : { *(.dynsym) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynsym*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.hash*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-/*
- * (c) Copyright 2011 by Tigris Elektronik GmbH
- *
- * Author:
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#include <command.h>
-#include <environment.h>
-#include <linux/stddef.h>
-#include <malloc.h>
-#include <search.h>
-#include <errno.h>
-#include <ext4fs.h>
-
-char *env_name_spec = "EXT4";
-
-env_t *env_ptr;
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int env_init(void)
-{
- /* use default */
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 1;
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_SAVEENV
-int saveenv(void)
-{
- env_t env_new;
- ssize_t len;
- char *res;
- block_dev_desc_t *dev_desc = NULL;
- int dev = EXT4_ENV_DEVICE;
- int part = EXT4_ENV_PART;
- int err;
-
- res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
- if (len < 0) {
- error("Cannot export environment: errno = %d\n", errno);
- return 1;
- }
-
- dev_desc = get_dev(EXT4_ENV_INTERFACE, dev);
- if (dev_desc == NULL) {
- printf("Failed to find %s%d\n",
- EXT4_ENV_INTERFACE, dev);
- return 1;
- }
-
- err = ext4_register_device(dev_desc, part);
- if (err) {
- printf("Failed to register %s%d:%d\n",
- EXT4_ENV_INTERFACE, dev, part);
- return 1;
- }
-
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
- err = ext4fs_write(EXT4_ENV_FILE, (void *)&env_new, sizeof(env_t));
- ext4fs_close();
- if (err == -1) {
- printf("\n** Unable to write \"%s\" from %s%d:%d **\n",
- EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);
- return 1;
- }
-
- puts("done\n");
- return 0;
-}
-#endif /* CONFIG_CMD_SAVEENV */
-
-void env_relocate_spec(void)
-{
- char buf[CONFIG_ENV_SIZE];
- block_dev_desc_t *dev_desc = NULL;
- int dev = EXT4_ENV_DEVICE;
- int part = EXT4_ENV_PART;
- int err;
-
- dev_desc = get_dev(EXT4_ENV_INTERFACE, dev);
- if (dev_desc == NULL) {
- printf("Failed to find %s%d\n",
- EXT4_ENV_INTERFACE, dev);
- set_default_env(NULL);
- return;
- }
-
- err = ext4_register_device(dev_desc, part);
- if (err) {
- printf("Failed to register %s%d:%d\n",
- EXT4_ENV_INTERFACE, dev, part);
- set_default_env(NULL);
- return;
- }
-
- err = ext4_read_file(EXT4_ENV_FILE, (uchar *)&buf, 0, CONFIG_ENV_SIZE);
- ext4fs_close();
-
- if (err == -1) {
- printf("\n** Unable to read \"%s\" from %s%d:%d **\n",
- EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);
- set_default_env(NULL);
- return;
- }
-
- env_import(buf, 1);
-}
+++ /dev/null
-/*
- * (C) Copyright 2013
- *
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <spl.h>
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-#include <version.h>
-#include <part.h>
-#include <fat.h>
-#include <ext4fs.h>
-
-/* should be implemented by board */
-extern void spl_block_device_init(void);
-
-block_dev_desc_t * spl_get_block_device(void)
-{
- block_dev_desc_t * device;
-
- spl_block_device_init();
-
- device = get_dev(CONFIG_SPL_BLOCKDEV_INTERFACE, CONFIG_SPL_BLOCKDEV_ID);
- if (!device) {
- printf("blk device %s%d not exists\n",
- CONFIG_SPL_BLOCKDEV_INTERFACE,
- CONFIG_SPL_BLOCKDEV_ID);
- hang();
- }
-
- return device;
-}
-
-#ifdef CONFIG_SPL_FAT_SUPPORT
-static int block_load_image_fat(const char *filename)
-{
- int err;
- struct image_header *header;
-
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header));
-
- err = file_fat_read(filename, header, sizeof(struct image_header));
- if (err <= 0)
- goto end;
-
- spl_parse_image_header(header);
-
- err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
-
-end:
- if (err <= 0)
- printf("spl: error reading image %s, err - %d\n",
- filename, err);
-
- return (err <= 0);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int block_load_image_fat_os(void)
-{
- int err;
-
- err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME,
- (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
- if (err <= 0) {
- return -1;
- }
-
- return block_load_image_fat(CONFIG_SPL_FAT_LOAD_KERNEL_NAME);
-}
-#endif
-
-void spl_block_load_image(void)
-{
- int err;
- block_dev_desc_t * device;
-
- device = spl_get_block_device();
- err = fat_register_device(device, CONFIG_BLOCKDEV_FAT_BOOT_PARTITION);
- if (err) {
- printf("spl: fat register err - %d\n", err);
- hang();
- }
-#ifdef CONFIG_SPL_OS_BOOT
- if (spl_start_uboot() || block_load_image_fat_os())
-#endif
- {
- err = block_load_image_fat(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
- if (err)
- hang();
- }
-}
-#elif defined(CONFIG_SPL_EXT4_SUPPORT) /* end CONFIG_SPL_FAT_SUPPORT */
-static int block_load_image_ext4(const char *filename)
-{
- int err;
- struct image_header *header;
-
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header));
-
- err = ext4_read_file(filename, header, 0, sizeof(struct image_header));
- if (err <= 0)
- goto end;
-
- spl_parse_image_header(header);
-
- err = ext4_read_file(filename, (u8 *)spl_image.load_addr, 0, 0);
-
-end:
- return (err <= 0);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int block_load_image_ext4_os(void)
-{
- int err;
-
- err = ext4_read_file(CONFIG_SPL_EXT4_LOAD_ARGS_NAME,
- (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, 0);
- if (err <= 0) {
- return -1;
- }
-
- return block_load_image_ext4(CONFIG_SPL_EXT4_LOAD_KERNEL_NAME);
-}
-#endif
-
-void spl_block_load_image(void)
-{
- int err;
- block_dev_desc_t * device;
-
- device = spl_get_block_device();
- err = ext4_register_device(device, CONFIG_BLOCKDEV_EXT4_BOOT_PARTITION);
- if (err) {
- hang();
- }
-#ifdef CONFIG_SPL_OS_BOOT
- if (spl_start_uboot() || block_load_image_ext4_os())
-#endif
- {
- err = block_load_image_ext4(CONFIG_SPL_EXT4_LOAD_PAYLOAD_NAME);
- if (err)
- hang();
- }
-}
-#else /* end CONFIG_SPL_EXT4_SUPPORT */
-static int block_load_image_raw(block_dev_desc_t * device, lbaint_t sector)
-{
- int n;
- u32 image_size_sectors;
- struct image_header *header;
-
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header));
-
- /* read image header to find the image size & load address */
- n = device->block_read(device->dev, sector, 1, header);
-
- if (n != 1) {
- printf("spl: blk read err\n");
- return 1;
- }
-
- spl_parse_image_header(header);
-
- /* convert size to sectors - round up */
- image_size_sectors = (spl_image.size + 512 - 1) / 512;
- n = device->block_read(device->dev, sector, image_size_sectors,
- (void *)spl_image.load_addr);
-
- if (n != image_size_sectors) {
- printf("spl: blk read err\n");
- return 1;
- }
- return 0;
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int block_load_image_raw_os(block_dev_desc_t * device)
-{
- int n;
-
- n = device->block_read(device->dev, CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTOR,
- CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS,
- (u32 *)CONFIG_SYS_SPL_ARGS_ADDR);
- /* flush cache after read */
- flush_cache(addr, CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS * 512);
-
- if (n != CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS) {
- printf("args blk read error\n");
- return -1;
- }
-
- return block_load_image_raw(device, CONFIG_SYS_BLOCK_RAW_MODE_KERNEL_SECTOR);
-}
-#endif
-
-void spl_block_load_image(void)
-{
- int err;
- block_dev_desc_t * device;
-
- device = spl_get_block_device();
-#ifdef CONFIG_SPL_OS_BOOT
- if (spl_start_uboot() || block_load_image_raw_os(device))
-#endif
- {
- err = block_load_image_raw(device,
- CONFIG_SYS_BLOCK_RAW_MODE_U_BOOT_SECTOR);
- if (err)
- hang();
- }
-}
-#endif /* CONFIG_SPL_FAT_SUPPORT */
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_OX820=y
-CONFIG_TARGET_OX820=y
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Oxford Semiconductor Ltd
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,`
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/clock.h>
-
-/**
- * SATA related definitions
- */
-#define ATA_PORT_CTL 0
-#define ATA_PORT_FEATURE 1
-#define ATA_PORT_NSECT 2
-#define ATA_PORT_LBAL 3
-#define ATA_PORT_LBAM 4
-#define ATA_PORT_LBAH 5
-#define ATA_PORT_DEVICE 6
-#define ATA_PORT_COMMAND 7
-
-/* The offsets to the SATA registers */
-#define SATA_ORB1_OFF 0
-#define SATA_ORB2_OFF 1
-#define SATA_ORB3_OFF 2
-#define SATA_ORB4_OFF 3
-#define SATA_ORB5_OFF 4
-
-#define SATA_FIS_ACCESS 11
-#define SATA_INT_STATUS_OFF 12 /* Read only */
-#define SATA_INT_CLR_OFF 12 /* Write only */
-#define SATA_INT_ENABLE_OFF 13 /* Read only */
-#define SATA_INT_ENABLE_SET_OFF 13 /* Write only */
-#define SATA_INT_ENABLE_CLR_OFF 14 /* Write only */
-#define SATA_VERSION_OFF 15
-#define SATA_CONTROL_OFF 23
-#define SATA_COMMAND_OFF 24
-#define SATA_PORT_CONTROL_OFF 25
-#define SATA_DRIVE_CONTROL_OFF 26
-
-/* The offsets to the link registers that are access in an asynchronous manner */
-#define SATA_LINK_DATA 28
-#define SATA_LINK_RD_ADDR 29
-#define SATA_LINK_WR_ADDR 30
-#define SATA_LINK_CONTROL 31
-
-/* SATA interrupt status register fields */
-#define SATA_INT_STATUS_EOC_RAW_BIT ( 0 + 16)
-#define SATA_INT_STATUS_ERROR_BIT ( 2 + 16)
-#define SATA_INT_STATUS_EOADT_RAW_BIT ( 1 + 16)
-
-/* SATA core command register commands */
-#define SATA_CMD_WRITE_TO_ORB_REGS 2
-#define SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND 4
-
-#define SATA_CMD_BUSY_BIT 7
-
-#define SATA_SCTL_CLR_ERR 0x00000316UL
-
-#define SATA_LBAL_BIT 0
-#define SATA_LBAM_BIT 8
-#define SATA_LBAH_BIT 16
-#define SATA_HOB_LBAH_BIT 24
-#define SATA_DEVICE_BIT 24
-#define SATA_NSECT_BIT 0
-#define SATA_HOB_NSECT_BIT 8
-#define SATA_LBA32_BIT 0
-#define SATA_LBA40_BIT 8
-#define SATA_FEATURE_BIT 16
-#define SATA_COMMAND_BIT 24
-#define SATA_CTL_BIT 24
-
-/* ATA status (7) register field definitions */
-#define ATA_STATUS_BSY_BIT 7
-#define ATA_STATUS_DRDY_BIT 6
-#define ATA_STATUS_DF_BIT 5
-#define ATA_STATUS_DRQ_BIT 3
-#define ATA_STATUS_ERR_BIT 0
-
-/* ATA device (6) register field definitions */
-#define ATA_DEVICE_FIXED_MASK 0xA0
-#define ATA_DEVICE_DRV_BIT 4
-#define ATA_DEVICE_DRV_NUM_BITS 1
-#define ATA_DEVICE_LBA_BIT 6
-
-/* ATA Command register initiated commands */
-#define ATA_CMD_INIT 0x91
-#define ATA_CMD_IDENT 0xEC
-
-#define SATA_STD_ASYNC_REGS_OFF 0x20
-#define SATA_SCR_STATUS 0
-#define SATA_SCR_ERROR 1
-#define SATA_SCR_CONTROL 2
-#define SATA_SCR_ACTIVE 3
-#define SATA_SCR_NOTIFICAION 4
-
-#define SATA_BURST_BUF_FORCE_EOT_BIT 0
-#define SATA_BURST_BUF_DATA_INJ_ENABLE_BIT 1
-#define SATA_BURST_BUF_DIR_BIT 2
-#define SATA_BURST_BUF_DATA_INJ_END_BIT 3
-#define SATA_BURST_BUF_FIFO_DIS_BIT 4
-#define SATA_BURST_BUF_DIS_DREQ_BIT 5
-#define SATA_BURST_BUF_DREQ_BIT 6
-
-#define SATA_OPCODE_MASK 0x3
-
-#define SATA_DMA_CHANNEL 0
-
-#define DMA_CTRL_STATUS (0x0)
-#define DMA_BASE_SRC_ADR (0x4)
-#define DMA_BASE_DST_ADR (0x8)
-#define DMA_BYTE_CNT (0xC)
-#define DMA_CURRENT_SRC_ADR (0x10)
-#define DMA_CURRENT_DST_ADR (0x14)
-#define DMA_CURRENT_BYTE_CNT (0x18)
-#define DMA_INTR_ID (0x1C)
-#define DMA_INTR_CLEAR_REG (DMA_CURRENT_SRC_ADR)
-
-#define DMA_CALC_REG_ADR(channel, register) ((volatile u32*)(DMA_BASE + ((channel) << 5) + (register)))
-
-#define DMA_CTRL_STATUS_FAIR_SHARE_ARB (1 << 0)
-#define DMA_CTRL_STATUS_IN_PROGRESS (1 << 1)
-#define DMA_CTRL_STATUS_SRC_DREQ_MASK (0x0000003C)
-#define DMA_CTRL_STATUS_SRC_DREQ_SHIFT (2)
-#define DMA_CTRL_STATUS_DEST_DREQ_MASK (0x000003C0)
-#define DMA_CTRL_STATUS_DEST_DREQ_SHIFT (6)
-#define DMA_CTRL_STATUS_INTR (1 << 10)
-#define DMA_CTRL_STATUS_NXT_FREE (1 << 11)
-#define DMA_CTRL_STATUS_RESET (1 << 12)
-#define DMA_CTRL_STATUS_DIR_MASK (0x00006000)
-#define DMA_CTRL_STATUS_DIR_SHIFT (13)
-#define DMA_CTRL_STATUS_SRC_ADR_MODE (1 << 15)
-#define DMA_CTRL_STATUS_DEST_ADR_MODE (1 << 16)
-#define DMA_CTRL_STATUS_TRANSFER_MODE_A (1 << 17)
-#define DMA_CTRL_STATUS_TRANSFER_MODE_B (1 << 18)
-#define DMA_CTRL_STATUS_SRC_WIDTH_MASK (0x00380000)
-#define DMA_CTRL_STATUS_SRC_WIDTH_SHIFT (19)
-#define DMA_CTRL_STATUS_DEST_WIDTH_MASK (0x01C00000)
-#define DMA_CTRL_STATUS_DEST_WIDTH_SHIFT (22)
-#define DMA_CTRL_STATUS_PAUSE (1 << 25)
-#define DMA_CTRL_STATUS_INTERRUPT_ENABLE (1 << 26)
-#define DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED (1 << 27)
-#define DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED (1 << 28)
-#define DMA_CTRL_STATUS_STARVE_LOW_PRIORITY (1 << 29)
-#define DMA_CTRL_STATUS_INTR_CLEAR_ENABLE (1 << 30)
-
-#define DMA_BYTE_CNT_MASK ((1 << 21) - 1)
-#define DMA_BYTE_CNT_WR_EOT_MASK (1 << 30)
-#define DMA_BYTE_CNT_RD_EOT_MASK (1 << 31)
-#define DMA_BYTE_CNT_BURST_MASK (1 << 28)
-
-#define MAKE_FIELD(value, num_bits, bit_num) (((value) & ((1 << (num_bits)) - 1)) << (bit_num))
-
-typedef enum oxnas_dma_mode {
- OXNAS_DMA_MODE_FIXED, OXNAS_DMA_MODE_INC
-} oxnas_dma_mode_t;
-
-typedef enum oxnas_dma_direction {
- OXNAS_DMA_TO_DEVICE, OXNAS_DMA_FROM_DEVICE
-} oxnas_dma_direction_t;
-
-/* The available buses to which the DMA controller is attached */
-typedef enum oxnas_dma_transfer_bus {
- OXNAS_DMA_SIDE_A, OXNAS_DMA_SIDE_B
-} oxnas_dma_transfer_bus_t;
-
-/* Direction of data flow between the DMA controller's pair of interfaces */
-typedef enum oxnas_dma_transfer_direction {
- OXNAS_DMA_A_TO_A, OXNAS_DMA_B_TO_A, OXNAS_DMA_A_TO_B, OXNAS_DMA_B_TO_B
-} oxnas_dma_transfer_direction_t;
-
-/* The available data widths */
-typedef enum oxnas_dma_transfer_width {
- OXNAS_DMA_TRANSFER_WIDTH_8BITS,
- OXNAS_DMA_TRANSFER_WIDTH_16BITS,
- OXNAS_DMA_TRANSFER_WIDTH_32BITS
-} oxnas_dma_transfer_width_t;
-
-/* The mode of the DMA transfer */
-typedef enum oxnas_dma_transfer_mode {
- OXNAS_DMA_TRANSFER_MODE_SINGLE, OXNAS_DMA_TRANSFER_MODE_BURST
-} oxnas_dma_transfer_mode_t;
-
-/* The available transfer targets */
-typedef enum oxnas_dma_dreq {
- OXNAS_DMA_DREQ_SATA = 0, OXNAS_DMA_DREQ_MEMORY = 15
-} oxnas_dma_dreq_t;
-
-typedef struct oxnas_dma_device_settings {
- unsigned long address_;
- unsigned fifo_size_; // Chained transfers must take account of FIFO offset at end of previous transfer
- unsigned char dreq_;
- unsigned read_eot_ :1;
- unsigned read_final_eot_ :1;
- unsigned write_eot_ :1;
- unsigned write_final_eot_ :1;
- unsigned bus_ :1;
- unsigned width_ :2;
- unsigned transfer_mode_ :1;
- unsigned address_mode_ :1;
- unsigned address_really_fixed_ :1;
-} oxnas_dma_device_settings_t;
-
-static const int MAX_NO_ERROR_LOOPS = 100000; /* 1 second in units of 10uS */
-static const int MAX_DMA_XFER_LOOPS = 300000; /* 30 seconds in units of 100uS */
-static const int MAX_DMA_ABORT_LOOPS = 10000; /* 0.1 second in units of 10uS */
-static const int MAX_SRC_READ_LOOPS = 10000; /* 0.1 second in units of 10uS */
-static const int MAX_SRC_WRITE_LOOPS = 10000; /* 0.1 second in units of 10uS */
-static const int MAX_NOT_BUSY_LOOPS = 10000; /* 1 second in units of 100uS */
-
-/* The internal SATA drive on which we should attempt to find partitions */
-static volatile u32* sata_regs_base[2] = { (volatile u32*) SATA_0_REGS_BASE,
- (volatile u32*) SATA_1_REGS_BASE,
-
-};
-static u32 wr_sata_orb1[2] = { 0, 0 };
-static u32 wr_sata_orb2[2] = { 0, 0 };
-static u32 wr_sata_orb3[2] = { 0, 0 };
-static u32 wr_sata_orb4[2] = { 0, 0 };
-
-#ifdef CONFIG_LBA48
-/* need keeping a record of NSECT LBAL LBAM LBAH ide_outb values for lba48 support */
-#define OUT_HISTORY_BASE ATA_PORT_NSECT
-#define OUT_HISTORY_MAX ATA_PORT_LBAH
-static unsigned char out_history[2][OUT_HISTORY_MAX - OUT_HISTORY_BASE + 1] = {};
-#endif
-
-static oxnas_dma_device_settings_t oxnas_sata_dma_settings = { .address_ =
- SATA_DATA_BASE, .fifo_size_ = 16, .dreq_ = OXNAS_DMA_DREQ_SATA,
- .read_eot_ = 0, .read_final_eot_ = 1, .write_eot_ = 0,
- .write_final_eot_ = 1, .bus_ = OXNAS_DMA_SIDE_B, .width_ =
- OXNAS_DMA_TRANSFER_WIDTH_32BITS, .transfer_mode_ =
- OXNAS_DMA_TRANSFER_MODE_BURST, .address_mode_ =
- OXNAS_DMA_MODE_FIXED, .address_really_fixed_ = 0 };
-
-oxnas_dma_device_settings_t oxnas_ram_dma_settings = { .address_ = 0,
- .fifo_size_ = 0, .dreq_ = OXNAS_DMA_DREQ_MEMORY, .read_eot_ = 1,
- .read_final_eot_ = 1, .write_eot_ = 1, .write_final_eot_ = 1,
- .bus_ = OXNAS_DMA_SIDE_A, .width_ =
- OXNAS_DMA_TRANSFER_WIDTH_32BITS, .transfer_mode_ =
- OXNAS_DMA_TRANSFER_MODE_BURST, .address_mode_ =
- OXNAS_DMA_MODE_FIXED, .address_really_fixed_ = 1 };
-
-static void xfer_wr_shadow_to_orbs(int device)
-{
- *(sata_regs_base[device] + SATA_ORB1_OFF) = wr_sata_orb1[device];
- *(sata_regs_base[device] + SATA_ORB2_OFF) = wr_sata_orb2[device];
- *(sata_regs_base[device] + SATA_ORB3_OFF) = wr_sata_orb3[device];
- *(sata_regs_base[device] + SATA_ORB4_OFF) = wr_sata_orb4[device];
-}
-
-static inline void device_select(int device)
-{
- /* master/slave has no meaning to SATA core */
-}
-
-static int disk_present[CONFIG_SYS_IDE_MAXDEVICE];
-
-#include <ata.h>
-
-unsigned char ide_inb(int device, int port)
-{
- unsigned char val = 0;
-
- /* Only permit accesses to disks found to be present during ide_preinit() */
- if (!disk_present[device]) {
- return ATA_STAT_FAULT;
- }
-
- device_select(device);
-
- switch (port) {
- case ATA_PORT_CTL:
- val = (*(sata_regs_base[device] + SATA_ORB4_OFF)
- & (0xFFUL << SATA_CTL_BIT)) >> SATA_CTL_BIT;
- break;
- case ATA_PORT_FEATURE:
- val = (*(sata_regs_base[device] + SATA_ORB2_OFF)
- & (0xFFUL << SATA_FEATURE_BIT)) >> SATA_FEATURE_BIT;
- break;
- case ATA_PORT_NSECT:
- val = (*(sata_regs_base[device] + SATA_ORB2_OFF)
- & (0xFFUL << SATA_NSECT_BIT)) >> SATA_NSECT_BIT;
- break;
- case ATA_PORT_LBAL:
- val = (*(sata_regs_base[device] + SATA_ORB3_OFF)
- & (0xFFUL << SATA_LBAL_BIT)) >> SATA_LBAL_BIT;
- break;
- case ATA_PORT_LBAM:
- val = (*(sata_regs_base[device] + SATA_ORB3_OFF)
- & (0xFFUL << SATA_LBAM_BIT)) >> SATA_LBAM_BIT;
- break;
- case ATA_PORT_LBAH:
- val = (*(sata_regs_base[device] + SATA_ORB3_OFF)
- & (0xFFUL << SATA_LBAH_BIT)) >> SATA_LBAH_BIT;
- break;
- case ATA_PORT_DEVICE:
- val = (*(sata_regs_base[device] + SATA_ORB3_OFF)
- & (0xFFUL << SATA_HOB_LBAH_BIT)) >> SATA_HOB_LBAH_BIT;
- val |= (*(sata_regs_base[device] + SATA_ORB1_OFF)
- & (0xFFUL << SATA_DEVICE_BIT)) >> SATA_DEVICE_BIT;
- break;
- case ATA_PORT_COMMAND:
- val = (*(sata_regs_base[device] + SATA_ORB2_OFF)
- & (0xFFUL << SATA_COMMAND_BIT)) >> SATA_COMMAND_BIT;
- val |= ATA_STAT_DRQ;
- break;
- default:
- printf("ide_inb() Unknown port = %d\n", port);
- break;
- }
-
- // printf("inb: %d:%01x => %02x\n", device, port, val);
-
- return val;
-}
-
-/**
- * Possible that ATA status will not become no-error, so must have timeout
- * @returns An int which is zero on error
- */
-static inline int wait_no_error(int device)
-{
- int status = 0;
-
- /* Check for ATA core error */
- if (*(sata_regs_base[device] + SATA_INT_STATUS_OFF)
- & (1 << SATA_INT_STATUS_ERROR_BIT)) {
- printf("wait_no_error() SATA core flagged error\n");
- } else {
- int loops = MAX_NO_ERROR_LOOPS;
- do {
- /* Check for ATA device error */
- if (!(ide_inb(device, ATA_PORT_COMMAND)
- & (1 << ATA_STATUS_ERR_BIT))) {
- status = 1;
- break;
- }
- udelay(10);
- } while (--loops);
-
- if (!loops) {
- printf("wait_no_error() Timed out of wait for SATA no-error condition\n");
- }
- }
-
- return status;
-}
-
-/**
- * Expect SATA command to always finish, perhaps with error
- * @returns An int which is zero on error
- */
-static inline int wait_sata_command_not_busy(int device)
-{
- /* Wait for data to be available */
- int status = 0;
- int loops = MAX_NOT_BUSY_LOOPS;
- do {
- if (!(*(sata_regs_base[device] + SATA_COMMAND_OFF)
- & (1 << SATA_CMD_BUSY_BIT))) {
- status = 1;
- break;
- }
- udelay(100);
- } while (--loops);
-
- if (!loops) {
- printf("wait_sata_command_not_busy() Timed out of wait for SATA command to finish\n");
- }
-
- return status;
-}
-
-void ide_outb(int device, int port, unsigned char val)
-{
- typedef enum send_method {
- SEND_NONE, SEND_SIMPLE, SEND_CMD, SEND_CTL,
- } send_method_t;
-
- /* Only permit accesses to disks found to be present during ide_preinit() */
- if (!disk_present[device]) {
- return;
- }
-
- // printf("outb: %d:%01x <= %02x\n", device, port, val);
-
- device_select(device);
-
-#ifdef CONFIG_LBA48
- if (port >= OUT_HISTORY_BASE && port <= OUT_HISTORY_MAX) {
- out_history[0][port - OUT_HISTORY_BASE] =
- out_history[1][port - OUT_HISTORY_BASE];
- out_history[1][port - OUT_HISTORY_BASE] = val;
- }
-#endif
- send_method_t send_regs = SEND_NONE;
- switch (port) {
- case ATA_PORT_CTL:
- wr_sata_orb4[device] &= ~(0xFFUL << SATA_CTL_BIT);
- wr_sata_orb4[device] |= (val << SATA_CTL_BIT);
- send_regs = SEND_CTL;
- break;
- case ATA_PORT_FEATURE:
- wr_sata_orb2[device] &= ~(0xFFUL << SATA_FEATURE_BIT);
- wr_sata_orb2[device] |= (val << SATA_FEATURE_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_NSECT:
- wr_sata_orb2[device] &= ~(0xFFUL << SATA_NSECT_BIT);
- wr_sata_orb2[device] |= (val << SATA_NSECT_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_LBAL:
- wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAL_BIT);
- wr_sata_orb3[device] |= (val << SATA_LBAL_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_LBAM:
- wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAM_BIT);
- wr_sata_orb3[device] |= (val << SATA_LBAM_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_LBAH:
- wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAH_BIT);
- wr_sata_orb3[device] |= (val << SATA_LBAH_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_DEVICE:
- wr_sata_orb1[device] &= ~(0xFFUL << SATA_DEVICE_BIT);
- wr_sata_orb1[device] |= (val << SATA_DEVICE_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_COMMAND:
- wr_sata_orb2[device] &= ~(0xFFUL << SATA_COMMAND_BIT);
- wr_sata_orb2[device] |= (val << SATA_COMMAND_BIT);
- send_regs = SEND_CMD;
-#ifdef CONFIG_LBA48
- if (val == ATA_CMD_READ_EXT || val == ATA_CMD_WRITE_EXT)
- {
- /* fill high bytes of LBA48 && NSECT */
- wr_sata_orb2[device] &= ~(0xFFUL << SATA_HOB_NSECT_BIT);
- wr_sata_orb2[device] |=
- (out_history[0][ATA_PORT_NSECT - OUT_HISTORY_BASE] << SATA_HOB_NSECT_BIT);
-
- wr_sata_orb3[device] &= ~(0xFFUL << SATA_HOB_LBAH_BIT);
- wr_sata_orb3[device] |=
- (out_history[0][ATA_PORT_LBAL - OUT_HISTORY_BASE] << SATA_HOB_LBAH_BIT);
-
- wr_sata_orb4[device] &= ~(0xFFUL << SATA_LBA32_BIT);
- wr_sata_orb4[device] |=
- (out_history[0][ATA_PORT_LBAM - OUT_HISTORY_BASE] << SATA_LBA32_BIT);
-
- wr_sata_orb4[device] &= ~(0xFFUL << SATA_LBA40_BIT);
- wr_sata_orb4[device] |=
- (out_history[0][ATA_PORT_LBAH - OUT_HISTORY_BASE] << SATA_LBA40_BIT);
- }
-#endif
- break;
- default:
- printf("ide_outb() Unknown port = %d\n", port);
- }
-
- u32 command;
- switch (send_regs) {
- case SEND_CMD:
- wait_sata_command_not_busy(device);
- command = *(sata_regs_base[device] + SATA_COMMAND_OFF);
- command &= ~SATA_OPCODE_MASK;
- command |= SATA_CMD_WRITE_TO_ORB_REGS;
- xfer_wr_shadow_to_orbs(device);
- wait_sata_command_not_busy(device);
- *(sata_regs_base[device] + SATA_COMMAND_OFF) = command;
- if (!wait_no_error(device)) {
- printf("ide_outb() Wait for ATA no-error timed-out\n");
- }
- break;
- case SEND_CTL:
- wait_sata_command_not_busy(device);
- command = *(sata_regs_base[device] + SATA_COMMAND_OFF);
- command &= ~SATA_OPCODE_MASK;
- command |= SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
- xfer_wr_shadow_to_orbs(device);
- wait_sata_command_not_busy(device);
- *(sata_regs_base[device] + SATA_COMMAND_OFF) = command;
- if (!wait_no_error(device)) {
- printf("ide_outb() Wait for ATA no-error timed-out\n");
- }
- break;
- default:
- break;
- }
-}
-
-static u32 encode_start(u32 ctrl_status)
-{
- return ctrl_status & ~DMA_CTRL_STATUS_PAUSE;
-}
-
-/* start a paused DMA transfer in channel 0 of the SATA DMA core */
-static void dma_start(void)
-{
- unsigned int reg;
- reg = readl(SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);
- reg = encode_start(reg);
- writel(reg, SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);
-}
-
-static unsigned long encode_control_status(
- oxnas_dma_device_settings_t* src_settings,
- oxnas_dma_device_settings_t* dst_settings)
-{
- unsigned long ctrl_status;
- oxnas_dma_transfer_direction_t direction;
-
- ctrl_status = DMA_CTRL_STATUS_PAUSE; // Paused
- ctrl_status |= DMA_CTRL_STATUS_FAIR_SHARE_ARB; // High priority
- ctrl_status |= (src_settings->dreq_ << DMA_CTRL_STATUS_SRC_DREQ_SHIFT); // Dreq
- ctrl_status |= (dst_settings->dreq_ << DMA_CTRL_STATUS_DEST_DREQ_SHIFT); // Dreq
- ctrl_status &= ~DMA_CTRL_STATUS_RESET; // !RESET
-
- // Use new interrupt clearing register
- ctrl_status |= DMA_CTRL_STATUS_INTR_CLEAR_ENABLE;
-
- // Setup the transfer direction and burst/single mode for the two DMA busses
- if (src_settings->bus_ == OXNAS_DMA_SIDE_A) {
- // Set the burst/single mode for bus A based on src device's settings
- if (src_settings->transfer_mode_
- == OXNAS_DMA_TRANSFER_MODE_BURST) {
- ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A;
- }
-
- if (dst_settings->bus_ == OXNAS_DMA_SIDE_A) {
- direction = OXNAS_DMA_A_TO_A;
- } else {
- direction = OXNAS_DMA_A_TO_B;
-
- // Set the burst/single mode for bus B based on dst device's settings
- if (dst_settings->transfer_mode_
- == OXNAS_DMA_TRANSFER_MODE_BURST) {
- ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B;
- }
- }
- } else {
- // Set the burst/single mode for bus B based on src device's settings
- if (src_settings->transfer_mode_
- == OXNAS_DMA_TRANSFER_MODE_BURST) {
- ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B;
- }
-
- if (dst_settings->bus_ == OXNAS_DMA_SIDE_A) {
- direction = OXNAS_DMA_B_TO_A;
-
- // Set the burst/single mode for bus A based on dst device's settings
- if (dst_settings->transfer_mode_
- == OXNAS_DMA_TRANSFER_MODE_BURST) {
- ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A;
- }
- } else {
- direction = OXNAS_DMA_B_TO_B;
- }
- }
- ctrl_status |= (direction << DMA_CTRL_STATUS_DIR_SHIFT);
-
- // Setup source address mode fixed or increment
- if (src_settings->address_mode_ == OXNAS_DMA_MODE_FIXED) {
- // Fixed address
- ctrl_status &= ~(DMA_CTRL_STATUS_SRC_ADR_MODE);
-
- // Set up whether fixed address is _really_ fixed
- if (src_settings->address_really_fixed_) {
- ctrl_status |= DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;
- }
- } else {
- // Incrementing address
- ctrl_status |= DMA_CTRL_STATUS_SRC_ADR_MODE;
- ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;
- }
-
- // Setup destination address mode fixed or increment
- if (dst_settings->address_mode_ == OXNAS_DMA_MODE_FIXED) {
- // Fixed address
- ctrl_status &= ~(DMA_CTRL_STATUS_DEST_ADR_MODE);
-
- // Set up whether fixed address is _really_ fixed
- if (dst_settings->address_really_fixed_) {
- ctrl_status |=
- DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;
- } else {
- ctrl_status &=
- ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;
- }
- } else {
- // Incrementing address
- ctrl_status |= DMA_CTRL_STATUS_DEST_ADR_MODE;
- ctrl_status &= ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;
- }
-
- // Set up the width of the transfers on the DMA buses
- ctrl_status |=
- (src_settings->width_ << DMA_CTRL_STATUS_SRC_WIDTH_SHIFT);
- ctrl_status |=
- (dst_settings->width_ << DMA_CTRL_STATUS_DEST_WIDTH_SHIFT);
-
- // Setup the priority arbitration scheme
- ctrl_status &= ~DMA_CTRL_STATUS_STARVE_LOW_PRIORITY; // !Starve low priority
-
- return ctrl_status;
-}
-
-static u32 encode_final_eot(oxnas_dma_device_settings_t* src_settings,
- oxnas_dma_device_settings_t* dst_settings,
- unsigned long length)
-{
- // Write the length, with EOT configuration for a final transfer
- unsigned long encoded = length;
- if (dst_settings->write_final_eot_) {
- encoded |= DMA_BYTE_CNT_WR_EOT_MASK;
- } else {
- encoded &= ~DMA_BYTE_CNT_WR_EOT_MASK;
- }
- if (src_settings->read_final_eot_) {
- encoded |= DMA_BYTE_CNT_RD_EOT_MASK;
- } else {
- encoded &= ~DMA_BYTE_CNT_RD_EOT_MASK;
- }
- /* if((src_settings->transfer_mode_) ||
- (src_settings->transfer_mode_)) {
- encoded |= DMA_BYTE_CNT_BURST_MASK;
- } else {
- encoded &= ~DMA_BYTE_CNT_BURST_MASK;
- }*/
- return encoded;
-}
-
-static void dma_start_write(const ulong* buffer, int num_bytes)
-{
- // Assemble complete memory settings
- oxnas_dma_device_settings_t mem_settings = oxnas_ram_dma_settings;
- mem_settings.address_ = (unsigned long) buffer;
- mem_settings.address_mode_ = OXNAS_DMA_MODE_INC;
-
- writel(encode_control_status(&mem_settings, &oxnas_sata_dma_settings),
- SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);
- writel(mem_settings.address_, SATA_DMA_REGS_BASE + DMA_BASE_SRC_ADR);
- writel(oxnas_sata_dma_settings.address_,
- SATA_DMA_REGS_BASE + DMA_BASE_DST_ADR);
- writel(encode_final_eot(&mem_settings, &oxnas_sata_dma_settings,
- num_bytes),
- SATA_DMA_REGS_BASE + DMA_BYTE_CNT);
-
- dma_start();
-}
-
-static void dma_start_read(ulong* buffer, int num_bytes)
-{
- // Assemble complete memory settings
- oxnas_dma_device_settings_t mem_settings = oxnas_ram_dma_settings;
- mem_settings.address_ = (unsigned long) buffer;
- mem_settings.address_mode_ = OXNAS_DMA_MODE_INC;
-
- writel(encode_control_status(&oxnas_sata_dma_settings, &mem_settings),
- SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);
- writel(oxnas_sata_dma_settings.address_,
- SATA_DMA_REGS_BASE + DMA_BASE_SRC_ADR);
- writel(mem_settings.address_, SATA_DMA_REGS_BASE + DMA_BASE_DST_ADR);
- writel(encode_final_eot(&oxnas_sata_dma_settings, &mem_settings,
- num_bytes),
- SATA_DMA_REGS_BASE + DMA_BYTE_CNT);
-
- dma_start();
-}
-
-static inline int dma_busy(void)
-{
- return readl(SATA_DMA_REGS_BASE + DMA_CTRL_STATUS)
- & DMA_CTRL_STATUS_IN_PROGRESS;
-}
-
-static int wait_dma_not_busy(int device)
-{
- unsigned int cleanup_required = 0;
-
- /* Poll for DMA completion */
- int loops = MAX_DMA_XFER_LOOPS;
- do {
- if (!dma_busy()) {
- break;
- }
- udelay(100);
- } while (--loops);
-
- if (!loops) {
- printf("wait_dma_not_busy() Timed out of wait for DMA not busy\n");
- cleanup_required = 1;
- }
-
- if (cleanup_required) {
- /* Abort DMA to make sure it has finished. */
- unsigned int ctrl_status = readl(
- SATA_DMA_CHANNEL + DMA_CTRL_STATUS);
- ctrl_status |= DMA_CTRL_STATUS_RESET;
- writel(ctrl_status, SATA_DMA_CHANNEL + DMA_CTRL_STATUS);
-
- // Wait for the channel to become idle - should be quick as should
- // finish after the next AHB single or burst transfer
- loops = MAX_DMA_ABORT_LOOPS;
- do {
- if (!dma_busy()) {
- break;
- }
- udelay(10);
- } while (--loops);
-
- if (!loops) {
- printf("wait_dma_not_busy() Timed out of wait for DMA channel abort\n");
- } else {
- /* Successfully cleanup the DMA channel */
- cleanup_required = 0;
- }
-
- // Deassert reset for the channel
- ctrl_status = readl(SATA_DMA_CHANNEL + DMA_CTRL_STATUS);
- ctrl_status &= ~DMA_CTRL_STATUS_RESET;
- writel(ctrl_status, SATA_DMA_CHANNEL + DMA_CTRL_STATUS);
- }
-
- return !cleanup_required;
-}
-
-/**
- * Possible that ATA status will not become not-busy, so must have timeout
- */
-static unsigned int wait_not_busy(int device, unsigned long timeout_secs)
-{
- int busy = 1;
- unsigned long loops = (timeout_secs * 1000) / 50;
- do {
- // Test the ATA status register BUSY flag
- if (!((*(sata_regs_base[device] + SATA_ORB2_OFF)
- >> SATA_COMMAND_BIT) & (1UL << ATA_STATUS_BSY_BIT))) {
- /* Not busy, so stop polling */
- busy = 0;
- break;
- }
-
- // Wait for 50mS before sampling ATA status register again
- udelay(50000);
- } while (--loops);
-
- return busy;
-}
-
-void ide_output_data(int device, const ulong *sect_buf, int words)
-{
- /* Only permit accesses to disks found to be present during ide_preinit() */
- if (!disk_present[device]) {
- return;
- }
-
- /* Select the required internal SATA drive */
- device_select(device);
-
- /* Start the DMA channel sending data from the passed buffer to the SATA core */
- dma_start_write(sect_buf, words << 2);
-
- /* Don't know why we need this delay, but without it the wait for DMA not
- busy times soemtimes out, e.g. when saving environment to second disk */
- udelay(1000);
-
- /* Wait for DMA to finish */
- if (!wait_dma_not_busy(device)) {
- printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n",
- device);
- }
-
- /* Sata core should finish after DMA */
- if (wait_not_busy(device, 30)) {
- printf("Timed out of wait for SATA device %d to have BUSY clear\n",
- device);
- }
- if (!wait_no_error(device)) {
- printf("oxnas_sata_output_data() Wait for ATA no-error timed-out\n");
- }
-}
-
-
-#define SATA_DM_DBG1 (SATA_HOST_REGS_BASE + 0)
-#define SATA_DATACOUNT_PORT0 (SATA_HOST_REGS_BASE + 0x10)
-#define SATA_DATACOUNT_PORT1 (SATA_HOST_REGS_BASE + 0x14)
-#define SATA_DATA_MUX_RAM0 (SATA_HOST_REGS_BASE + 0x8000)
-#define SATA_DATA_MUX_RAM1 (SATA_HOST_REGS_BASE + 0xA000)
-/* Sata core debug1 register bits */
-#define SATA_CORE_PORT0_DATA_DIR_BIT 20
-#define SATA_CORE_PORT1_DATA_DIR_BIT 21
-#define SATA_CORE_PORT0_DATA_DIR (1 << SATA_CORE_PORT0_DATA_DIR_BIT)
-#define SATA_CORE_PORT1_DATA_DIR (1 << SATA_CORE_PORT1_DATA_DIR_BIT)
-
-/**
- * Ref bug-6320
- *
- * This code is a work around for a DMA hardware bug that will repeat the
- * penultimate 8-bytes on some reads. This code will check that the amount
- * of data transferred is a multiple of 512 bytes, if not the in it will
- * fetch the correct data from a buffer in the SATA core and copy it into
- * memory.
- *
- */
-static void sata_bug_6320_workaround(int port, ulong *candidate)
-{
- int is_read;
- int quads_transferred;
- int remainder;
- int sector_quads_remaining;
-
- /* Only want to apply fix to reads */
- is_read = !(*((unsigned long*) SATA_DM_DBG1)
- & (port ? SATA_CORE_PORT1_DATA_DIR : SATA_CORE_PORT0_DATA_DIR));
-
- /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
- transferred (datacount_port register counts quads transferred) */
- quads_transferred = *((unsigned long*) (
- port ? SATA_DATACOUNT_PORT1 : SATA_DATACOUNT_PORT0));
-
- remainder = quads_transferred & 0x7f;
- sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
-
- if (is_read && (sector_quads_remaining == 2)) {
- debug("SATA read fixup, only transfered %d quads, "
- "sector_quads_remaining %d, port %d\n",
- quads_transferred, sector_quads_remaining, port);
-
- int total_len = ATA_SECT_SIZE;
- ulong *sata_data_ptr = (void*) (
- port ? SATA_DATA_MUX_RAM1 : SATA_DATA_MUX_RAM0)
- + ((total_len - 8) % 2048);
-
- *candidate = *sata_data_ptr;
- *(candidate + 1) = *(sata_data_ptr + 1);
- }
-}
-
-
-void ide_input_data(int device, ulong *sect_buf, int words)
-{
- /* Only permit accesses to disks found to be present during ide_preinit() */
- if (!disk_present[device]) {
- return;
- }
-
- /* Select the required internal SATA drive */
- device_select(device);
-
- /* Start the DMA channel receiving data from the SATA core into the passed buffer */
- dma_start_read(sect_buf, words << 2);
-
- /* Sata core should finish before DMA */
- if (wait_not_busy(device, 30)) {
- printf("Timed out of wait for SATA device %d to have BUSY clear\n",
- device);
- }
- if (!wait_no_error(device)) {
- printf("oxnas_sata_output_data() Wait for ATA no-error timed-out\n");
- }
-
- /* Wait for DMA to finish */
- if (!wait_dma_not_busy(device)) {
- printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n",
- device);
- }
-
- if (words == ATA_SECTORWORDS)
- sata_bug_6320_workaround(device, sect_buf + words - 2);
-}
-
-static u32 scr_read(int device, unsigned int sc_reg)
-{
- /* Setup adr of required register. std regs start eight into async region */
- *(sata_regs_base[device] + SATA_LINK_RD_ADDR) = sc_reg
- * 4+ SATA_STD_ASYNC_REGS_OFF;
-
- /* Wait for data to be available */
- int loops = MAX_SRC_READ_LOOPS;
- do {
- if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) {
- break;
- }
- udelay(10);
- } while (--loops);
-
- if (!loops) {
- printf("scr_read() Timed out of wait for read completion\n");
- }
-
- /* Read the data from the async register */
- return *(sata_regs_base[device] + SATA_LINK_DATA);
-}
-
-static void scr_write(int device, unsigned int sc_reg, u32 val)
-{
- /* Setup the data for the write */
- *(sata_regs_base[device] + SATA_LINK_DATA) = val;
-
- /* Setup adr of required register. std regs start eight into async region */
- *(sata_regs_base[device] + SATA_LINK_WR_ADDR) = sc_reg
- * 4+ SATA_STD_ASYNC_REGS_OFF;
-
- /* Wait for data to be written */
- int loops = MAX_SRC_WRITE_LOOPS;
- do {
- if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) {
- break;
- }
- udelay(10);
- } while (--loops);
-
- if (!loops) {
- printf("scr_write() Timed out of wait for write completion\n");
- }
-}
-extern void workaround5458(void);
-
-#define PHY_LOOP_COUNT 25 /* Wait for upto 5 seconds for PHY to be found */
-#define LOS_AND_TX_LVL 0x2988
-#define TX_ATTEN 0x55629
-
-static int phy_reset(int device)
-{
- int phy_status = 0;
- int loops = 0;
-
- scr_write(device, (0x60 - SATA_STD_ASYNC_REGS_OFF) / 4, LOS_AND_TX_LVL);
- scr_write(device, (0x70 - SATA_STD_ASYNC_REGS_OFF) / 4, TX_ATTEN);
-
- /* limit it to Gen-1 SATA (1.5G) */
- scr_write(device, SATA_SCR_CONTROL, 0x311); /* Issue phy wake & core reset */
- scr_read(device, SATA_SCR_STATUS); /* Dummy read; flush */
- udelay(1000);
- scr_write(device, SATA_SCR_CONTROL, 0x310); /* Issue phy wake & clear core reset */
-
- /* Wait for upto 5 seconds for PHY to become ready */
- do {
- udelay(200000);
- if ((scr_read(device, SATA_SCR_STATUS) & 0xf) == 3) {
- scr_write(device, SATA_SCR_ERROR, ~0);
- phy_status = 1;
- break;
- }
- //printf("No SATA PHY found status:0x%x\n", scr_read(device, SATA_SCR_STATUS));
- } while (++loops < PHY_LOOP_COUNT);
-
- if (phy_status) {
- udelay(500000); /* wait half a second */
- }
-
- return phy_status;
-}
-
-#define FIS_LOOP_COUNT 25 /* Wait for upto 5 seconds for FIS to be received */
-static int wait_FIS(int device)
-{
- int status = 0;
- int loops = 0;
-
- do {
- udelay(200000);
- if (ide_inb(device, ATA_PORT_NSECT) > 0) {
- status = 1;
- break;
- }
- } while (++loops < FIS_LOOP_COUNT);
-
- return status;
-}
-
-
-#define SATA_PHY_ASIC_STAT (0x44900000)
-#define SATA_PHY_ASIC_DATA (0x44900004)
-
-/**
- * initialise functions and macros for ASIC implementation
- */
-#define PH_GAIN 2
-#define FR_GAIN 3
-#define PH_GAIN_OFFSET 6
-#define FR_GAIN_OFFSET 8
-#define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
-#define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
-#define USE_INT_SETTING (1<<5)
-
-#define CR_READ_ENABLE (1<<16)
-#define CR_WRITE_ENABLE (1<<17)
-#define CR_CAP_DATA (1<<18)
-
-static void wait_cr_ack(void)
-{
- while ((readl(SATA_PHY_ASIC_STAT) >> 16) & 0x1f)
- /* wait for an ack bit to be set */;
-}
-
-static unsigned short read_cr(unsigned short address)
-{
- writel(address, SATA_PHY_ASIC_STAT);
- wait_cr_ack();
- writel(CR_READ_ENABLE, SATA_PHY_ASIC_DATA);
- wait_cr_ack();
- return readl(SATA_PHY_ASIC_STAT);
-}
-
-static void write_cr(unsigned short data, unsigned short address)
-{
- writel(address, SATA_PHY_ASIC_STAT);
- wait_cr_ack();
- writel((data | CR_CAP_DATA), SATA_PHY_ASIC_DATA);
- wait_cr_ack();
- writel(CR_WRITE_ENABLE, SATA_PHY_ASIC_DATA);
- wait_cr_ack();
- return;
-}
-
-void workaround5458(void)
-{
- unsigned i;
-
- for (i = 0; i < 2; i++) {
- unsigned short rx_control = read_cr(0x201d + (i << 8));
- rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
- rx_control |= PH_GAIN << PH_GAIN_OFFSET;
- rx_control |= FR_GAIN << FR_GAIN_OFFSET;
- rx_control |= USE_INT_SETTING;
- write_cr(rx_control, 0x201d + (i << 8));
- }
-}
-
-int ide_preinit(void)
-{
- int num_disks_found = 0;
-
- /* Initialise records of which disks are present to all present */
- int i;
- for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; i++) {
- disk_present[i] = 1;
- }
-
- /* Block reset SATA and DMA cores */
- reset_block(SYS_CTRL_RST_SATA, 1);
- reset_block(SYS_CTRL_RST_SATA_LINK, 1);
- reset_block(SYS_CTRL_RST_SATA_PHY, 1);
- reset_block(SYS_CTRL_RST_SGDMA, 1);
-
- /* Enable clocks to SATA and DMA cores */
- enable_clock(SYS_CTRL_CLK_SATA);
- enable_clock(SYS_CTRL_CLK_DMA);
-
- udelay(5000);
- reset_block(SYS_CTRL_RST_SATA_PHY, 0);
- udelay(50);
- reset_block(SYS_CTRL_RST_SATA, 0);
- reset_block(SYS_CTRL_RST_SATA_LINK, 0);
- udelay(50);
- reset_block(SYS_CTRL_RST_SGDMA, 0);
- udelay(100);
- /* Apply the Synopsis SATA PHY workarounds */
- workaround5458();
- udelay(10000);
-
- /* disable and clear core interrupts */
- *((unsigned long*) SATA_HOST_REGS_BASE + SATA_INT_ENABLE_CLR_OFF) =
- ~0UL;
- *((unsigned long*) SATA_HOST_REGS_BASE + SATA_INT_CLR_OFF) = ~0UL;
-
- int device;
- for (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) {
- int found = 0;
- int retries = 1;
-
- /* Disable SATA interrupts */
- *(sata_regs_base[device] + SATA_INT_ENABLE_CLR_OFF) = ~0UL;
-
- /* Clear any pending SATA interrupts */
- *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL;
-
- do {
- /* clear sector count register for FIS detection */
- ide_outb(device, ATA_PORT_NSECT, 0);
-
- /* Get the PHY working */
- if (!phy_reset(device)) {
- printf("SATA PHY not ready for device %d\n",
- device);
- break;
- }
-
- if (!wait_FIS(device)) {
- printf("No FIS received from device %d\n",
- device);
- } else {
- if ((scr_read(device, SATA_SCR_STATUS) & 0xf)
- == 0x3) {
- if (wait_not_busy(device, 30)) {
- printf("Timed out of wait for SATA device %d to have BUSY clear\n",
- device);
- } else {
- ++num_disks_found;
- found = 1;
- }
- } else {
- printf("No SATA device %d found, PHY status = 0x%08x\n",
- device,
- scr_read(
- device,
- SATA_SCR_STATUS));
- }
- break;
- }
- } while (retries--);
-
- /* Record whether disk is present, so won't attempt to access it later */
- disk_present[device] = found;
- }
-
- /* post disk detection clean-up */
- for (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) {
- if (disk_present[device]) {
- /* set as ata-5 (28-bit) */
- *(sata_regs_base[device] + SATA_DRIVE_CONTROL_OFF) =
- 0UL;
-
- /* clear phy/link errors */
- scr_write(device, SATA_SCR_ERROR, ~0);
-
- /* clear host errors */
- *(sata_regs_base[device] + SATA_CONTROL_OFF) |=
- SATA_SCTL_CLR_ERR;
-
- /* clear interrupt register as this clears the error bit in the IDE
- status register */
- *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL;
- }
- }
-
- return !num_disks_found;
-}
-
+++ /dev/null
-/*
- * drivers/usb/host/ehci-oxnas.c
- *
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sysctl.h>
-#include <asm/arch/clock.h>
-
-#include "ehci.h"
-
-static struct ehci_hcor *ghcor;
-
-static int start_oxnas_usb_ehci(void)
-{
-#ifdef CONFIG_USB_PLLB_CLK
- reset_block(SYS_CTRL_RST_PLLB, 0);
- enable_clock(SYS_CTRL_CLK_REF600);
-
- writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV),
- SEC_CTRL_PLLB_CTRL0);
- /* 600MHz pllb divider for 12MHz */
- writel(PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0), SEC_CTRL_PLLB_DIV_CTRL);
-#else
- /* ref 300 divider for 12MHz */
- writel(REF300_DIV_INT(25) | REF300_DIV_FRAC(0), SYS_CTRL_REF300_DIV);
-#endif
-
- /* Ensure the USB block is properly reset */
- reset_block(SYS_CTRL_RST_USBHS, 1);
- reset_block(SYS_CTRL_RST_USBHS, 0);
-
- reset_block(SYS_CTRL_RST_USBHSPHYA, 1);
- reset_block(SYS_CTRL_RST_USBHSPHYA, 0);
-
- reset_block(SYS_CTRL_RST_USBHSPHYB, 1);
- reset_block(SYS_CTRL_RST_USBHSPHYB, 0);
-
- /* Force the high speed clock to be generated all the time, via serial
- programming of the USB HS PHY */
- writel((2UL << USBHSPHY_TEST_ADD) |
- (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
-
- writel((1UL << USBHSPHY_TEST_CLK) |
- (2UL << USBHSPHY_TEST_ADD) |
- (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
-
- writel((0xfUL << USBHSPHY_TEST_ADD) |
- (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
-
- writel((1UL << USBHSPHY_TEST_CLK) |
- (0xfUL << USBHSPHY_TEST_ADD) |
- (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
-
-#ifdef CONFIG_USB_PLLB_CLK /* use pllb clock */
- writel(USB_CLK_INTERNAL | USB_INT_CLK_PLLB, SYS_CTRL_USB_CTRL);
-#else /* use ref300 derived clock */
- writel(USB_CLK_INTERNAL | USB_INT_CLK_REF300, SYS_CTRL_USB_CTRL);
-#endif
- /* Enable the clock to the USB block */
- enable_clock(SYS_CTRL_CLK_USBHS);
-
- return 0;
-}
-int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
- struct ehci_hcor **hcor)
-{
- start_oxnas_usb_ehci();
- *hccr = (struct ehci_hccr *)(USB_HOST_BASE + 0x100);
- *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
- HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
- ghcor = *hcor;
- return 0;
-}
-
-int ehci_hcd_stop(int index)
-{
- reset_block(SYS_CTRL_RST_USBHS, 1);
- disable_clock(SYS_CTRL_CLK_USBHS);
- return 0;
-}
-
-extern void __ehci_set_usbmode(int index);
-void ehci_set_usbmode(int index)
-{
- #define or_txttfill_tuning _reserved_1_[0]
- u32 tmp;
-
- __ehci_set_usbmode(index);
-
- tmp = ehci_readl(&ghcor->or_txfilltuning);
- tmp &= ~0x00ff0000;
- tmp |= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes) */
- tmp |= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/
- ehci_writel(&ghcor->or_txfilltuning, tmp);
-
- tmp = ehci_readl(&ghcor->or_txttfill_tuning);
- tmp |= 0x2; /* set sheduler overhead to 2 * 6.333us */
- ehci_writel(&ghcor->or_txttfill_tuning, tmp);
-}
+++ /dev/null
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_ARM1136
-#define CONFIG_OX820
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-
-/* make cmd_ide.c quiet when compile */
-#define __io
-
-/*#define CONFIG_ARCH_CPU_INIT*/
-/*#define CONFIG_DISPLAY_CPUINFO*/
-/*#define CONFIG_DISPLAY_BOARDINFO*/
-/*#define CONFIG_BOARD_EARLY_INIT_F*/
-/*#define CONFIG_SKIP_LOWLEVEL_INIT*/
-
-/* mem */
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_MIN_SDRAM_SIZE (128 * 1024 * 1024) /* 128 MB */
-#define CONFIG_MAX_SDRAM_SIZE (512 * 1024 * 1024) /* 512 MB */
-#define CONFIG_SRAM_BASE 0x50000000
-#define CONFIG_SRAM_SIZE (64 * 1024)
-
-/* need do dma so better keep dcache off */
-#define CONFIG_SYS_DCACHE_OFF
-
-/* clock */
-#define CONFIG_PLLA_FREQ_MHZ 800
-#define CONFIG_RPSCLK 6250000
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_CLK_FREQ CONFIG_RPSCLK
-#define CONFIG_SYS_TIMERBASE TIMER1_BASE
-#define CONFIG_TIMER_PRESCALE TIMER_PRESCALE_16
-
-/* serial */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK CONFIG_RPSCLK
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_NS16550_COM1 UART_1_BASE
-#define CONFIG_CONS_INDEX 1
-
-/* ide */
-#define CONFIG_SYS_ATA_BASE_ADDR 0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-#define CONFIG_SYS_ATA_ALT_OFFSET 0
-#define CONFIG_IDE_PLX
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_IDE_PREINIT
-#define CONFIG_LBA48
-
-/* nand */
-#define CONFIG_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE STATIC_CS0_BASE
-#define NAND_CLE_ADDR_PIN 19
-#define NAND_ALE_ADDR_PIN 18
-#define MTDPARTS_DEFAULT "mtdparts=41000000.nand:" \
- "14m(boot)," \
- "-(ubi)"
-#define MTDIDS_DEFAULT "nand0=41000000.nand"
-#define UBIPART_DEFAULT "ubi"
-
-/* net */
-#define CONFIG_DESIGNWARE_ETH
-#define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_MII
-#define CONFIG_CMD_MII
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_ICPLUS
-
-/* spl */
-#ifdef CONFIG_SPL_BUILD
-#define USE_DL_PREFIX /* rename malloc free etc, so we can override them */
-#endif
-
-#if defined(CONFIG_BOOT_FROM_NAND) || defined(CONFIG_BOOT_FROM_SATA)
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_TEXT_BASE 0x50000000
-#define CONFIG_SPL_STACK (CONFIG_SRAM_BASE + (48 * 1024))
-#define CONFIG_SPL_DISPLAY_PRINT
-#define CONFIG_SPL_BSS_DRAM_START 0x65000000
-#define CONFIG_SPL_BSS_DRAM_SIZE 0x01000000
-#define CONFIG_SPL_MALLOC_START 0x66000000
-#endif
-
-#if defined(CONFIG_BOOT_FROM_NAND)
-#define CONFIG_SPL_NAND_SUPPORT
-#define BOOT_DEVICE_TYPE "NAND"
-#define BOOT_DEVICE_NAND 0xfeedbacc
-#define CONFIG_SPL_BOOT_DEVICE BOOT_DEVICE_NAND
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_NAND_SOFTECC
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 6
-#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
- 48, 49, 50, 51, 52, 53, 54, 55, \
- 56, 57, 58, 59, 60, 61, 62, 63}
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-/* pages per erase block */
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
-/* nand spl use 1 erase block, and use bit to byte encode for reliability */
-#define CONFIG_SPL_MAX_SIZE (128 * 1024 / 8)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
-/* spl kernel load is not enabled */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
-#define CONFIG_CMD_SPL_NAND_OFS 0
-#define CONFIG_CMD_SPL_WRITE_SIZE 1024
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
-/* CONFIG_BOOT_FROM_NAND end */
-
-#elif defined(CONFIG_BOOT_FROM_SATA)
-#define CONFIG_SPL_BLOCK_SUPPORT
-#define BOOT_DEVICE_TYPE "SATA"
-#define BOOT_DEVICE_BLOCK 860202
-#define CONFIG_SPL_BOOT_DEVICE BOOT_DEVICE_BLOCK
-#define CONFIG_SPL_MAX_SIZE (36 * 1024)
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_BLOCKDEV_INTERFACE "ide"
-#define CONFIG_SPL_BLOCKDEV_ID 0
-
-#ifdef CONFIG_BOOT_FROM_FAT /* u-boot in fat partition */
-
-#define CONFIG_SPL_FAT_SUPPORT
-
-#define CONFIG_BLOCKDEV_FAT_BOOT_PARTITION 1 /* first partition */
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" /* u-boot file name */
-/* enable U-Boot Falcon Mode */
-#define CONFIG_CMD_SPL
-#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "bootargs.bin" /* boot parameters */
-#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "falcon.img" /* kernel */
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
-
-#elif CONFIG_BOOT_FROM_EXT4
-
-#define CONFIG_SPL_EXT4_SUPPORT
-#define CONFIG_BLOCKDEV_EXT4_BOOT_PARTITION 1 /* first partition */
-#define CONFIG_SPL_EXT4_LOAD_PAYLOAD_NAME "/boot/u-boot.img" /* u-boot file name */
-/* enable U-Boot Falcon Mode */
-#define CONFIG_CMD_SPL
-#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_EXT4_LOAD_ARGS_NAME "/boot/bootargs.bin" /* boot parameters */
-#define CONFIG_SPL_EXT4_LOAD_KERNEL_NAME "/boot/falcon.img" /* kernel */
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
-
-#else /* u-boot in raw sectors */
-
-#define CONFIG_SYS_BLOCK_RAW_MODE_U_BOOT_SECTOR 1024
-/* spl kernel load is not enabled */
-#define CONFIG_SYS_BLOCK_RAW_MODE_KERNEL_SECTOR 4096
-#define CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTOR 0
-#define CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS (1024 / 512)
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
-
-#endif /* CONFIG_BOOT_FROM_FAT */
-/* CONFIG_BOOT_FROM_SATA end */
-
-#else
-/* generic, no spl support */
-#endif
-
-/* boot */
-#define CONFIG_IDENT_STRING " for OXNAS"
-#define CONFIG_MACH_TYPE MACH_TYPE_OXNAS
-#ifndef CONFIG_SPL_BUILD
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-#endif
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_DEFAULT_CONSOLE_PARM "console=ttyS0,115200n8 earlyprintk=serial"
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_AUTOLOAD "no"
-
-#define CONFIG_DEFAULT_CONSOLE CONFIG_DEFAULT_CONSOLE_PARM "\0"
-#define CONFIG_BOOTARGS CONFIG_DEFAULT_CONSOLE_PARM
-#define CONFIG_BOOTCOMMAND "run nandboot"
-#define CONFIG_BOOT_RETRY_TIME -1
-#define CONFIG_RESET_TO_RETRY 60
-
-#define CONFIG_NETCONSOLE
-#define CONFIG_IPADDR 192.168.50.100
-#define CONFIG_SERVERIP 192.168.50.59
-
-/* A sane default configuration...
- * When booting without a valid environment in ubi, first to loading and booting
- * the kernel image directly above U-Boot, maybe both were loaded there by
- * another bootloader.
- * Also use that same offset (0x90000) to load the rescue image later on (by
- * adding it onto the flash address where U-Boot is supposed to be stored by
- * the legacy loader, 0x440000, resulting in offset 0x4d0000 on the flash).
- * When coming up with a valid environment in ubi, first try to load the
- * kernel from a ubi volume kernel, if that fails, fallback to the rescue
- * image stored in boot partition. As a last resort try booting via
- * DHCP/TFTP.
- * In case there is no valid environment, first probe for a uimage in ram left
- * behind by the first bootloader on a tftp boot.
- * If that fails, switch to normal boot order and save environment.
- * The loader is supposed to be written to flash at offset 0x440000 and loaded to
- * RAM at 0x64000000
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "load_kernel_ubi=ubi readvol 0x62000000 kernel;\0" \
- "load_kernel_rescue=nand read 0x62000000 0x4e0000 0x400000;\0" \
- "load_kernel_dhcp=dhcp 0x62000000 oxnas-rescue.bin;\0" \
- "boot_kernel=bootm 0x62000000;\0" \
- "boot_ubi=run load_kernel_ubi && run boot_kernel;\0" \
- "boot_rescue=run load_kernel_rescue && run boot_kernel;\0" \
- "boot_dhcp=run load_kernel_dhcp && run boot_kernel;\0" \
- "normalboot=run boot_ubi; run boot_rescue; run boot_dhcp;\0" \
- "firstboot=bootm 0x640a0000; setenv bootcmd run normalboot; " \
- "setenv firstboot; saveenv; run bootcmd; \0" \
- "bootcmd=run firstboot; \0" \
- "console=" CONFIG_DEFAULT_CONSOLE \
- "bootargs=" CONFIG_BOOTARGS "\0" \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
-
-/* env */
-#if defined(CONFIG_BOOT_FROM_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x000C0000
-#define CONFIG_ENV_SIZE 0x00020000
-#define CONFIG_ENV_OFFSET_REDUND 0x00100000
-#define CONFIG_ENV_SIZE_REDUND 0x00020000
-#define CONFIG_ENV_RANGE (CONFIG_ENV_SIZE * 2)
-/* CONFIG_BOOT_FROM_NAND end */
-
-#elif defined(CONFIG_BOOT_FROM_SATA)
-#ifdef CONFIG_BOOT_FROM_EXT4
-#define CONFIG_ENV_IS_IN_EXT4
-#define CONFIG_START_IDE
-#define EXT4_ENV_INTERFACE "ide"
-#define EXT4_ENV_DEVICE 0
-#define EXT4_ENV_PART 1
-#define EXT4_ENV_FILE "/boot/u-boot.env"
-#define CONFIG_ENV_SIZE (16 * 1024)
-#else
-#define CONFIG_ENV_IS_IN_FAT
-#define CONFIG_START_IDE
-#define FAT_ENV_INTERFACE "ide"
-#define FAT_ENV_DEVICE 0
-#define FAT_ENV_PART 1
-#define FAT_ENV_FILE "u-boot.env"
-#define CONFIG_ENV_SIZE (16 * 1024)
-#endif
-/* CONFIG_BOOT_FROM_SATA end */
-#elif defined(CONFIG_BOOT_FROM_SATA)
-
-#else
-/* generic */
-#define CONFIG_ENV_IS_IN_UBI 1
-#define CONFIG_ENV_UBI_PART UBIPART_DEFAULT
-#define CONFIG_ENV_UBI_VOLUME "ubootenv"
-#define CONFIG_ENV_UBI_VOLUME_REDUND "ubootenv2"
-#define CONFIG_ENV_SIZE (16 * 1024)
-#endif
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_TEXT_BASE 0x64000000
-#define CONFIG_SYS_INIT_SP_ADDR 0x65000000
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "OX820 # "
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size*/
-#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE
-
-/* usb */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_USB_EHCI
-#define CONFIG_EHCI_IS_TDI
-/* #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x3F */
-#define CONFIG_USB_PLLB_CLK
-#define CONFIG_USB_EHCI_OXNAS
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_USB_STORAGE
-#endif
-#define CONFIG_CMD_USB
-
-/* cmds */
-#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_ENV_FLAGS
-
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PXE
-
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CMD_EXT4_WRITE
-#endif
-
-#define CONFIG_CMD_ZIP
-#define CONFIG_CMD_UNZIP
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_HASH
-#define CONFIG_CMD_INI
-#define CONFIG_CMD_GETTIME
-#define CONFIG_CMD_BOOTMENU
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_BOOTZ
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
-/* for CONFIG_CMD_MTDPARTS */
-#define CONFIG_MTD_DEVICE
-/* for CONFIG_CMD_UBI */
-#define CONFIG_MTD_PARTITIONS
-/* for CONFIG_CMD_UBI */
-#define CONFIG_RBTREE
-
-/* optional, for CONFIG_CMD_BOOTM & required by CONFIG_CMD_UBIFS */
-#define CONFIG_LZO
-#define CONFIG_LZMA
-#define CONFIG_BZIP2
-
-/* for CONFIG_CMD_ZIP */
-#define CONFIG_GZIP_COMPRESSED
-/* for CONFIG_CMD_MD5SUM */
-#define CONFIG_MD5
-#define CONFIG_MD5SUM_VERIFY
-/* enable CONFIG_CMD_HASH's verification feature */
-#define CONFIG_HASH_VERIFY
-#define CONFIG_REGEX
-/* for CONFIG_CMD_BOOTMENU & CONFIG_CMD_PXE */
-#define CONFIG_MENU
-
-/* for new FIT uImage format generated in OpenWrt */
-#define CONFIG_FIT
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* J J Larworthy 27 September 2006 */
-
-/* file to read the boot sector of a dis and the loaded image and report
- * if the boot rom would accept the data as intact and suitable for use
- */
-
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/errno.h>
-
-#include <fcntl.h>
-#include <unistd.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <assert.h>
-
-extern uint32_t crc32(uint32_t, const unsigned char *, unsigned int);
-
-#define NUMBER_VECTORS 12
-struct {
- unsigned int start_vector[NUMBER_VECTORS];
- char code[4];
- unsigned int header_length;
- unsigned int reserved[3];
- unsigned int length;
- unsigned int img_CRC;
- unsigned int CRC;
-} img_header;
-
-void print_usage(void)
-{
- printf("update_header file.bin\n");
-}
-
-void print_header(void)
-{
- int i;
-
- printf("vectors in header\n");
- for (i = 0; i < NUMBER_VECTORS; i++) {
- printf("%d:0x%08x\n", i, img_header.start_vector[i]);
- }
- printf("length:%8x\nimg_CRC:0x%08x\nHeader CRC:0x%08x\n",
- img_header.length, img_header.img_CRC, img_header.CRC);
-}
-
-int main(int argc, char **argv)
-{
- int in_file;
- int status;
- int unsigned crc;
- int file_length;
- int len;
-
- struct stat file_stat;
-
- void *executable;
-
- in_file = open(argv[1], O_RDWR);
-
- if (in_file < 0) {
- printf("failed to open file:%s\n", argv[optind]);
- return -ENOENT;
- }
-
- status = fstat(in_file, &file_stat);
-
- /* read header and obtain size of image */
- status = read(in_file, &img_header, sizeof(img_header));
-
- file_length = file_stat.st_size - sizeof(img_header);
-
- if (img_header.length != file_length) {
- printf("size in header:%d, size of file: %d\n",
- img_header.length, file_length);
- }
- img_header.length = file_length;
-
- /* read working image and CRC */
- executable = malloc(file_length);
-
- status = read(in_file, executable, file_length);
-
- if (status != file_length) {
- printf("Failed to load image\n");
- free(executable);
- return -ENOENT;
- }
-
- /* verify image CRC */
- crc = crc32(0, (const unsigned char *) executable, img_header.length);
-
- if (crc != img_header.img_CRC) {
- printf("New Image CRC:0x%08x, hdr:0x%08x\n", crc,
- img_header.img_CRC);
- img_header.img_CRC = crc;
- }
- memcpy(img_header.code, "BOOT", 4);
- img_header.header_length = sizeof(img_header);
-
- /* check header CRC */
- crc = crc32(0, (const unsigned char *) &img_header,
- sizeof(img_header) - sizeof(unsigned int));
- if (crc != img_header.CRC) {
- printf("New header CRC - crc:0x%08x hdr:0x%08x\n", crc,
- img_header.CRC);
- img_header.CRC = crc;
- }
-
- /* re-write the file */
- status = lseek(in_file, 0, SEEK_SET);
- if (status != 0) {
- printf("failed to rewind\n");
- free(executable);
- return 1;
- }
- len = write(in_file, &img_header, sizeof(img_header));
- assert(len == sizeof(img_header));
- len = write(in_file, executable, file_length);
- assert(len == file_length);
- close(in_file);
- free(executable);
-
- return 0;
-}
+++ /dev/null
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=oxnas
-BOARDNAME:=PLXTECH/Oxford NAS782x/OX8xx
-SUBTARGETS:=ox810se ox820
-FEATURES:=gpio ramdisk rtc squashfs
-DEVICE_TYPE:=nas
-
-KERNEL_PATCHVER:=5.15
-
-include $(INCLUDE_DIR)/target.mk
-
-DEFAULT_PACKAGES += \
- kmod-button-hotplug kmod-input-gpio-keys-polled \
- kmod-leds-gpio uboot-envtools
-
-KERNELNAME:=zImage dtbs
-
-$(eval $(call BuildTarget))
+++ /dev/null
-
-. /lib/functions/uci-defaults.sh
-. /lib/functions/system.sh
-
-bootloader_cmdline_var() {
- local param
- local pval
- for arg in $(cat /proc/device-tree/chosen/bootloader-args); do
- param="$(echo $arg | cut -d'=' -f 1)"
- pval="$(echo $arg | cut -d'=' -f 2-)"
-
- if [ "$param" = "$1" ]; then
- echo "$pval"
- fi
- done
-}
-
-legacy_boot_mac_adr() {
- local macstr
- local oIFS
- macstr="$(bootloader_cmdline_var mac_adr)"
- oIFS="$IFS"
- IFS=","
- set -- $macstr
- printf "%02x:%02x:%02x:%02x:%02x:%02x" $1 $2 $3 $4 $5 $6
- IFS="$oIFS"
-}
-
-oxnas_setup_interfaces()
-{
- local board="$1"
-
- case $board in
- *)
- ucidef_set_interface_lan "eth0" "dhcp"
- ;;
- esac
-}
-
-oxnas_setup_macs()
-{
- local board="$1"
- local lan_mac=""
-
- case $board in
- shuttle,kd20)
- lan_mac="$(legacy_boot_mac_adr)"
- ;;
- esac
-
- [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
-}
-
-board_config_update
-board=$(board_name)
-oxnas_setup_interfaces $board
-oxnas_setup_macs $board
-board_config_flush
-
-exit 0
+++ /dev/null
-#!/bin/sh /etc/rc.common
-
-START=99
-
-get_irq() {
- local name="$1"
- grep -m 1 "$name" /proc/interrupts | cut -d: -f1 | sed 's, *,,'
-}
-
-set_irq_affinity() {
- local name="$1"
- local val="$2"
- local irq="$(get_irq "$name")"
- [ -n "$irq" ] || return
- echo "$val" > "/proc/irq/$irq/smp_affinity"
-}
-
-start() {
- set_irq_affinity ehci_hcd 2
- set_irq_affinity xhci_hcd 2
- set_irq_affinity sata 2
-}
+++ /dev/null
-REQUIRE_IMAGE_METADATA=1
-
-platform_check_image() {
- return 0
-}
-
-platform_do_upgrade() {
- nand_do_upgrade $1
-}
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_CPU_AUTO=y
-# CONFIG_ARCH_MULTI_V4 is not set
-# CONFIG_ARCH_MULTI_V4T is not set
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OXNAS=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEBUG_FS=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_BLK_PM=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=64
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_OXNAS=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_ARM926T=y
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LZ4=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DWMAC_GENERIC=y
-CONFIG_DWMAC_OXNAS=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_ELF_CORE=y
-CONFIG_FAT_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FREEZER=y
-CONFIG_FWNODE_MDIO=y
-# CONFIG_FW_CACHE is not set
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HWMON=y
-CONFIG_HZ_FIXED=0
-CONFIG_ICPLUS_PHY=y
-CONFIG_INET_DIAG=y
-# CONFIG_INET_DIAG_DESTROY is not set
-# CONFIG_INET_RAW_DIAG is not set
-CONFIG_INET_TCP_DIAG=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_KALLSYMS=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KEXEC=y
-CONFIG_KEXEC_CORE=y
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_ONESHOT=y
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LZ4_COMPRESS=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_OX810SE is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OXNAS_RPS_TIMER=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-CONFIG_PCS_XPCS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHY_OXNAS=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_OXNAS=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_OXNAS=y
-CONFIG_PPS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_TRACE=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RD_LZ4=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_LZO=y
-CONFIG_RD_XZ=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_OXNAS=y
-CONFIG_SCHED_DEBUG=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SOCK_DIAG=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VERSATILE_FPGA_IRQ=y
-CONFIG_VERSATILE_FPGA_IRQ_NR=4
-CONFIG_VFAT_FS=y
-# CONFIG_VFP is not set
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_WATCHDOG is not set
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_INFLATE=y
+++ /dev/null
-/dts-v1/;
-
-#include "ox820.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Akitio MyCloud";
-
- compatible = "akitio,mycloud", "oxsemi,ox820";
-
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- /* 128Mbytes DDR */
- reg = <0x60000000 0x8000000>;
- };
-
- aliases {
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- };
-
- i2c-gpio {
- compatible = "i2c-gpio";
- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH
- &gpio1 10 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c>;
- i2c-gpio,delay-us = <10>;
- #address-cells = <1>;
- #size-cells = <0>;
- ds1307: rtc@68 {
- compatible = "dallas,ds1307";
- reg = <0x68>;
- };
- };
-
- keys {
- compatible = "gpio-keys-polled";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_buttons>;
- #address-cells = <1>;
- #size-cells = <0>;
- poll-interval = <100>;
- power {
- label = "power";
- gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- };
- reset {
- label = "reset";
- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_leds>;
- led_status: status {
- label = "akitio:red:status";
- gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio-poweroff {
- compatible = "gpio-poweroff";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_poweroff>;
- gpios = <&gpio1 13 GPIO_SINGLE_ENDED>;
- };
-};
-
-&pinctrl {
- pinctrl_i2c: i2c-0 {
- i2c {
- pins = "gpio41", "gpio42"; /* MF_B9, MF_B10 */
- function = "gpio";
- /* ToDo: find a way to set debounce for those pins */
- };
- };
- pinctrl_buttons: buttons-0 {
- buttons {
- pins = "gpio11", "gpio38"; /* MF_A11, MF_B6 GPIO */
- function = "gpio";
- };
- };
- pinctrl_leds: leds-0 {
- leds {
- pins = "gpio29"; /* MF_A29 GPIO */
- function = "gpio";
- };
- };
- pinctrl_poweroff: poweroff-0 {
- poweroff {
- pins = "gpio45"; /* MF_B13 GPIO */
- function = "gpio";
- };
- };
-};
-
-&uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&nandc {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "hamming";
-
- partition@0 {
- label = "boot";
- reg = <0x0 0x26c0000>;
- };
-
- partition@26c0000 {
- label = "ubi";
- reg = <0x26c0000 0xd940000>;
- };
- };
-};
-
-ða {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
-};
-
-&ehci {
- status = "okay";
-};
-
-&sata {
- status = "okay";
- nr-ports = <2>;
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
+++ /dev/null
-/*
- * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3
- *
- *
- * Licensed under GPLv2 or later
- */
-
-/dts-v1/;
-#include "ox820.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Cloud Engines PogoPlug Pro";
-
- compatible = "cloudengines,pogoplugpro", "oxsemi,ox820";
-
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- /* 128Mbytes DDR */
- reg = <0x60000000 0x8000000>;
- };
-
- aliases {
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- led-boot = &led_status;
- led-failsafe = &led_warn;
- led-running = &led_act;
- led-upgrade = &led_warn;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status: blue {
- label = "pogoplug:blue";
- gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- led_warn: orange {
- label = "pogoplug:orange";
- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- led_act: green {
- label = "pogoplug:green";
- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
- };
-};
-
-&uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&nandc {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "hamming";
-
- partition@0 {
- label = "stage1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "u-boot";
- reg = <0x00040000 0x00380000>;
- read-only;
- };
-
- partition@3c0000 {
- label = "u-boot-env";
- reg = <0x003c0000 0x00080000>;
- };
-
- partition@440000 {
- label = "kernel";
- reg = <0x00440000 0x009c0000>;
- };
-
- partition@e00000 {
- label = "ubi";
- reg = <0x00e00000 0x07200000>;
- };
- };
-};
-
-&ehci {
- status = "okay";
-};
-
-ða {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
-};
-
-&sata {
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
+++ /dev/null
-/dts-v1/;
-
-#include "ox820.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "MitraStar Technology Corp. STG-212";
-
- compatible = "mitrastar,stg-212", "oxsemi,ox820";
-
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- /* 128Mbytes DDR */
- reg = <0x60000000 0x8000000>;
- };
-
- aliases {
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- led-boot = &led_status;
- led-failsafe = &led_warn;
- led-running = &led_status;
- led-upgrade = &led_warn;
- };
-
- keys {
- compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
- poll-interval = <100>;
-
- reset {
- label = "reset";
- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- copy {
- label = "copy";
- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_COPY>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- led_status: status {
- label = "zyxel:blue:status";
- gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- };
- led_warn: status2 {
- label = "zyxel:red:status";
- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
- };
- copy {
- label = "zyxel:orange:copy";
- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
- trigger-sources = <&ehci_port1>, <&ehci_port2>;
- linux,default-trigger = "usbport";
- };
- };
-
- i2c-gpio {
- compatible = "i2c-gpio";
- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH
- &gpio1 10 GPIO_ACTIVE_HIGH>;
- i2c-gpio,delay-us = <10>;
- };
-};
-
-&uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&nandc {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "hamming";
-
- partition@0 {
- label = "stage1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "u-boot";
- reg = <0x00040000 0x00380000>;
- read-only;
- };
-
- partition@3c0000 {
- label = "u-boot-env";
- reg = <0x003c0000 0x00080000>;
- };
-
- partition@440000 {
- label = "kernel";
- reg = <0x00440000 0x009c0000>;
- };
-
- partition@e00000 {
- label = "ubi";
- reg = <0x00e00000 0x07200000>;
- };
- };
-};
-
-ða {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
-};
-
-&ehci {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
+++ /dev/null
-/dts-v1/;
-
-#include "ox820.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- model = "Shuttle KD20";
-
- compatible = "shuttle,kd20", "oxsemi,ox820";
-
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- /* 256Mbytes DDR */
- reg = <0x60000000 0x10000000>;
- };
-
- aliases {
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- led-boot = &led_status;
- led-failsafe = &led_warn;
- led-running = &led_status;
- led-upgrade = &led_warn;
- };
-
- thermal-zones {
- chassis-thermal {
- /* Poll every 20 seconds */
- polling-delay = <20000>;
- /* Poll every 2nd second when cooling */
- polling-delay-passive = <2000>;
-
- thermal-sensors = <&hdd0_temp>, <&hdd1_temp>;
-
- trips {
- chassis_alert0: chassis-alert0 {
- /* At 43 degrees turn on fan */
- temperature = <43000>;
- hysteresis = <3000>;
- type = "active";
- };
-
- chassis_alert1: chassis-alert1 {
- /* At 60 degrees emergency shutdown */
- temperature = <60000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&chassis_alert0>;
- cooling-device = <&system_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
- i2c-gpio {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 9 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
- sck-gpios = <&gpio1 10 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <10>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc0: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
- };
-
- keys {
- compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
- poll-interval = <100>;
-
- power {
- label = "power";
- gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- };
- reset {
- label = "reset";
- gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- eject1 {
- label = "eject1";
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_EJECTCD>;
- };
- eject2 {
- label = "eject2";
- gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
- linux,code = <162>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- led_status: status {
- label = "kd20:blue:status";
- gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
- };
- led_warn: status2 {
- label = "kd20:red:status";
- gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
- };
- hdd1blue {
- label = "kd20:blue:hdd1";
- gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "ata1";
- };
- hdd1red {
- label = "kd20:red:hdd1";
- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- };
- hdd2blue {
- label = "kd20:blue:hdd2";
- gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "ata2";
- };
- hdd2red {
- label = "kd20:red:hdd2";
- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- };
- usb {
- label = "kd20:blue:usb";
- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- trigger-sources = <&ehci_port1>, <&ehci_port2>;
- linux,default-trigger = "usbport";
- };
- };
-
- beeper: beeper {
- compatible = "gpio-beeper";
- gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
- };
-
- system_fan: gpio-fan {
- compatible = "gpio-fan";
- gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = <0 0
- 3000 1>;
- #cooling-cells = <2>;
- };
-
- gpio-poweroff {
- compatible = "gpio-poweroff";
- gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&nandc {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "hamming";
-
- partition@0 {
- label = "stage1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "u-boot";
- reg = <0x00040000 0x001e0000>;
- read-only;
- };
-
- partition@220000 {
- label = "u-boot-env";
- reg = <0x00220000 0x00020000>;
- };
-
- partition@240000 {
- label = "initrd";
- reg = <0x00240000 0x00600000>;
- };
-
- partition@840000 {
- label = "kernel";
- reg = <0x00840000 0x007C0000>;
- };
-
- partition@e00000 {
- label = "ubi";
- reg = <0x01000000 0x07000000>;
- };
- };
-};
-
-ða {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
-};
-
-&ehci {
- status = "okay";
-};
-
-&sata {
- status = "okay";
- nr-ports = <2>;
-
- hdd0_temp: sata-port@0 {
- reg = <0>;
- #thermal-sensor-cells = <0>;
- };
-
- hdd1_temp: sata-port@1 {
- reg = <1>;
- #thermal-sensor-cells = <0>;
- };
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
+++ /dev/null
-/* linux/include/asm-arm/arch-oxnas/uncompress.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#define OXNAS_UART1_BASE 0x44200000
-
-static inline void putc(int c)
-{
- static volatile unsigned char *uart =
- (volatile unsigned char *)OXNAS_UART1_BASE;
-
- while (!(uart[5] & 0x20)) { /* LSR reg THR empty bit */
- barrier();
- }
- uart[0] = c; /* THR register */
-}
-
-static inline void flush(void)
-{
-}
-
-#define arch_decomp_setup()
-
-#define arch_decomp_wdog()
-
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
+++ /dev/null
-/*
- * sata_oxnas
- * A driver to interface the 934 based sata core present in the ox820
- * with libata and scsi
- * based on ox820 sata code by:
- * Copyright (c) 2007 Oxford Semiconductor Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/ata.h>
-#include <linux/libata.h>
-#include <linux/of_platform.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/clk.h>
-#include <linux/reset.h>
-
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include <linux/version.h>
-
-static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
-{
- u32 val = readl_relaxed(p);
-
- val &= ~mask;
- writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
-{
- u32 val = readl_relaxed(p);
-
- val |= mask;
- writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_value_mask(void __iomem *p,
- unsigned mask, unsigned new_value)
-{
- /* TODO sanity check mask & new_value = new_value */
- u32 val = readl_relaxed(p);
-
- val &= ~mask;
- val |= new_value;
- writel_relaxed(val, p);
-}
-
-/* sgdma request structure */
-struct sgdma_request {
- volatile u32 qualifier;
- volatile u32 control;
- dma_addr_t src_pa;
- dma_addr_t dst_pa;
-} __packed __aligned(4);
-
-
-/* Controller information */
-enum {
- SATA_OXNAS_MAX_PRD = 63,
- SATA_OXNAS_DMA_SIZE = SATA_OXNAS_MAX_PRD *
- sizeof(struct ata_bmdma_prd) +
- sizeof(struct sgdma_request),
- SATA_OXNAS_MAX_PORTS = 2,
- /** The different Oxsemi SATA core version numbers */
- SATA_OXNAS_CORE_VERSION = 0x1f3,
- SATA_OXNAS_IRQ_FLAG = IRQF_SHARED,
- SATA_OXNAS_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
- ATA_FLAG_NO_ATAPI /*| ATA_FLAG_NCQ*/),
- SATA_OXNAS_QUEUE_DEPTH = 32,
-
- SATA_OXNAS_DMA_BOUNDARY = 0xFFFFFFFF,
-};
-
-
-/*
- * SATA Port Registers
- */
-enum {
- /** sata host port register offsets */
- ORB1 = 0x00,
- ORB2 = 0x04,
- ORB3 = 0x08,
- ORB4 = 0x0C,
- ORB5 = 0x10,
- MASTER_STATUS = 0x10,
- FIS_CTRL = 0x18,
- FIS_DATA = 0x1C,
- INT_STATUS = 0x30,
- INT_CLEAR = 0x30,
- INT_ENABLE = 0x34,
- INT_DISABLE = 0x38,
- VERSION = 0x3C,
- SATA_CONTROL = 0x5C,
- SATA_COMMAND = 0x60,
- HID_FEATURES = 0x64,
- PORT_CONTROL = 0x68,
- DRIVE_CONTROL = 0x6C,
- /** These registers allow access to the link layer registers
- that reside in a different clock domain to the processor bus */
- LINK_DATA = 0x70,
- LINK_RD_ADDR = 0x74,
- LINK_WR_ADDR = 0x78,
- LINK_CONTROL = 0x7C,
- /* window control */
- WIN1LO = 0x80,
- WIN1HI = 0x84,
- WIN2LO = 0x88,
- WIN2HI = 0x8C,
- WIN0_CONTROL = 0x90,
-};
-
-/** sata port register bits */
-enum{
- /**
- * commands to issue in the master status to tell it to move shadow ,
- * registers to the actual device ,
- */
- SATA_OPCODE_MASK = 0x00000007,
- CMD_WRITE_TO_ORB_REGS_NO_COMMAND = 0x4,
- CMD_WRITE_TO_ORB_REGS = 0x2,
- CMD_SYNC_ESCAPE = 0x7,
- CMD_CORE_BUSY = (1 << 7),
- CMD_DRIVE_SELECT_SHIFT = 12,
- CMD_DRIVE_SELECT_MASK = (0xf << CMD_DRIVE_SELECT_SHIFT),
-
- /** interrupt bits */
- INT_END_OF_CMD = 1 << 0,
- INT_LINK_SERROR = 1 << 1,
- INT_ERROR = 1 << 2,
- INT_LINK_IRQ = 1 << 3,
- INT_REG_ACCESS_ERR = 1 << 7,
- INT_BIST_FIS = 1 << 11,
- INT_MASKABLE = INT_END_OF_CMD |
- INT_LINK_SERROR |
- INT_ERROR |
- INT_LINK_IRQ |
- INT_REG_ACCESS_ERR |
- INT_BIST_FIS,
- INT_WANT = INT_END_OF_CMD |
- INT_LINK_SERROR |
- INT_REG_ACCESS_ERR |
- INT_ERROR,
- INT_ERRORS = INT_LINK_SERROR |
- INT_REG_ACCESS_ERR |
- INT_ERROR,
-
- /** raw interrupt bits, unmaskable, but do not generate interrupts */
- RAW_END_OF_CMD = INT_END_OF_CMD << 16,
- RAW_LINK_SERROR = INT_LINK_SERROR << 16,
- RAW_ERROR = INT_ERROR << 16,
- RAW_LINK_IRQ = INT_LINK_IRQ << 16,
- RAW_REG_ACCESS_ERR = INT_REG_ACCESS_ERR << 16,
- RAW_BIST_FIS = INT_BIST_FIS << 16,
- RAW_WANT = INT_WANT << 16,
- RAW_ERRORS = INT_ERRORS << 16,
-
- /**
- * variables to write to the device control register to set the current
- * device, ie. master or slave.
- */
- DR_CON_48 = 2,
- DR_CON_28 = 0,
-
- SATA_CTL_ERR_MASK = 0x00000016,
-
-};
-
-/* ATA SGDMA register offsets */
-enum {
- SGDMA_CONTROL = 0x0,
- SGDMA_STATUS = 0x4,
- SGDMA_REQUESTPTR = 0x8,
- SGDMA_RESETS = 0xC,
- SGDMA_CORESIZE = 0x10,
-};
-
-/* DMA controller register offsets */
-enum {
- DMA_CONTROL = 0x0,
- DMA_CORESIZE = 0x20,
-
- DMA_CONTROL_RESET = (1 << 12),
-};
-
-enum {
- /* see DMA core docs for the values. Out means from memory (bus A) out
- * to disk (bus B) */
- SGDMA_REQCTL0OUT = 0x0497c03d,
- /* burst mode disabled when no micro code used */
- SGDMA_REQCTL0IN = 0x0493a3c1,
- SGDMA_REQCTL1OUT = 0x0497c07d,
- SGDMA_REQCTL1IN = 0x0497a3c5,
- SGDMA_CONTROL_NOGO = 0x3e,
- SGDMA_CONTROL_GO = SGDMA_CONTROL_NOGO | 1,
- SGDMA_ERRORMASK = 0x3f,
- SGDMA_BUSY = 0x80,
-
- SGDMA_RESETS_CTRL = 1 << 0,
- SGDMA_RESETS_ARBT = 1 << 1,
- SGDMA_RESETS_AHB = 1 << 2,
- SGDMA_RESETS_ALL = SGDMA_RESETS_CTRL |
- SGDMA_RESETS_ARBT |
- SGDMA_RESETS_AHB,
-
- /* Final EOTs */
- SGDMA_REQQUAL = 0x00220001,
-
-};
-
-/** SATA core register offsets */
-enum {
- DM_DBG1 = 0x000,
- RAID_SET = 0x004,
- DM_DBG2 = 0x008,
- DATACOUNT_PORT0 = 0x010,
- DATACOUNT_PORT1 = 0x014,
- CORE_INT_STATUS = 0x030,
- CORE_INT_CLEAR = 0x030,
- CORE_INT_ENABLE = 0x034,
- CORE_INT_DISABLE = 0x038,
- CORE_REBUILD_ENABLE = 0x050,
- CORE_FAILED_PORT_R = 0x054,
- DEVICE_CONTROL = 0x068,
- EXCESS = 0x06C,
- RAID_SIZE_LOW = 0x070,
- RAID_SIZE_HIGH = 0x074,
- PORT_ERROR_MASK = 0x078,
- IDLE_STATUS = 0x07C,
- RAID_CONTROL = 0x090,
- DATA_PLANE_CTRL = 0x0AC,
- CORE_DATAPLANE_STAT = 0x0b8,
- PROC_PC = 0x100,
- CONFIG_IN = 0x3d8,
- PROC_START = 0x3f0,
- PROC_RESET = 0x3f4,
- UCODE_STORE = 0x1000,
- RAID_WP_BOT_LOW = 0x1FF0,
- RAID_WP_BOT_HIGH = 0x1FF4,
- RAID_WP_TOP_LOW = 0x1FF8,
- RAID_WP_TOP_HIGH = 0x1FFC,
- DATA_MUX_RAM0 = 0x8000,
- DATA_MUX_RAM1 = 0xA000,
- PORT_SIZE = 0x10000,
-};
-
-enum {
- /* Sata core debug1 register bits */
- CORE_PORT0_DATA_DIR_BIT = 20,
- CORE_PORT1_DATA_DIR_BIT = 21,
- CORE_PORT0_DATA_DIR = 1 << CORE_PORT0_DATA_DIR_BIT,
- CORE_PORT1_DATA_DIR = 1 << CORE_PORT1_DATA_DIR_BIT,
-
- /** sata core control register bits */
- SCTL_CLR_ERR = 0x00003016,
- RAID_CLR_ERR = 0x0000011e,
-
- /* Interrupts direct from the ports */
- NORMAL_INTS_WANTED = 0x00000303,
-
- /* shift these left by port number */
- COREINT_HOST = 0x00000001,
- COREINT_END = 0x00000100,
- CORERAW_HOST = COREINT_HOST << 16,
- CORERAW_END = COREINT_END << 16,
-
- /* Interrupts from the RAID controller only */
- RAID_INTS_WANTED = 0x00008300,
-
- /* The bits in the IDLE_STATUS that, when set indicate an idle core */
- IDLE_CORES = (1 << 18) | (1 << 19),
-
- /* Data plane control error-mask mask and bit, these bit in the data
- * plane control mask out errors from the ports that prevent the SGDMA
- * care from sending an interrupt */
- DPC_ERROR_MASK = 0x00000300,
- DPC_ERROR_MASK_BIT = 0x00000100,
- /* enable jbod micro-code */
- DPC_JBOD_UCODE = 1 << 0,
- DPC_FIS_SWCH = 1 << 1,
-
- /** Device Control register bits */
- DEVICE_CONTROL_DMABT = 1 << 4,
- DEVICE_CONTROL_ABORT = 1 << 2,
- DEVICE_CONTROL_PAD = 1 << 3,
- DEVICE_CONTROL_PADPAT = 1 << 16,
- DEVICE_CONTROL_PRTRST = 1 << 8,
- DEVICE_CONTROL_RAMRST = 1 << 12,
- DEVICE_CONTROL_ATA_ERR_OVERRIDE = 1 << 28,
-
- /** oxsemi HW raid modes */
- OXNASSATA_NOTRAID = 0,
- OXNASSATA_RAID0 = 1,
- OXNASSATA_RAID1 = 2,
- /** OX820 specific HW-RAID register values */
- RAID_TWODISKS = 3,
- UNKNOWN_MODE = ~0,
-
- CONFIG_IN_RESUME = 2,
-};
-
-/* SATA PHY Registers */
-enum {
- PHY_STAT = 0x00,
- PHY_DATA = 0x04,
-};
-
-enum {
- STAT_READ_VALID = (1 << 21),
- STAT_CR_ACK = (1 << 20),
- STAT_CR_READ = (1 << 19),
- STAT_CR_WRITE = (1 << 18),
- STAT_CAP_DATA = (1 << 17),
- STAT_CAP_ADDR = (1 << 16),
-
- STAT_ACK_ANY = STAT_CR_ACK |
- STAT_CR_READ |
- STAT_CR_WRITE |
- STAT_CAP_DATA |
- STAT_CAP_ADDR,
-
- CR_READ_ENABLE = (1 << 16),
- CR_WRITE_ENABLE = (1 << 17),
- CR_CAP_DATA = (1 << 18),
-};
-
-enum {
- /* Link layer registers */
- SERROR_IRQ_MASK = 5,
-};
-
-enum {
- OXNAS_SATA_SOFTRESET = 1,
- OXNAS_SATA_REINIT = 2,
-};
-
-enum {
- OXNAS_SATA_UCODE_RAID0,
- OXNAS_SATA_UCODE_RAID1,
- OXNAS_SATA_UCODE_JBOD,
- OXNAS_SATA_UCODE_NONE,
-};
-
-enum {
- SATA_UNLOCKED,
- SATA_WRITER,
- SATA_READER,
- SATA_REBUILD,
- SATA_HWRAID,
- SATA_SCSI_STACK
-};
-
-typedef irqreturn_t (*oxnas_sata_isr_callback_t)(int, unsigned long, int);
-
-struct sata_oxnas_host_priv {
- void __iomem *port_base;
- void __iomem *dmactl_base;
- void __iomem *sgdma_base;
- void __iomem *core_base;
- void __iomem *phy_base;
- dma_addr_t dma_base;
- void __iomem *dma_base_va;
- size_t dma_size;
- int irq;
- int n_ports;
- int current_ucode;
- u32 port_frozen;
- u32 port_in_eh;
- struct clk *clk;
- struct reset_control *rst_sata;
- struct reset_control *rst_link;
- struct reset_control *rst_phy;
- spinlock_t phy_lock;
- spinlock_t core_lock;
- int core_locked;
- int reentrant_port_no;
- int hw_lock_count;
- int direct_lock_count;
- void *locker_uid;
- int current_locker_type;
- int scsi_nonblocking_attempts;
- oxnas_sata_isr_callback_t isr_callback;
- void *isr_arg;
- wait_queue_head_t fast_wait_queue;
- wait_queue_head_t scsi_wait_queue;
-};
-
-
-struct sata_oxnas_port_priv {
- void __iomem *port_base;
- void __iomem *dmactl_base;
- void __iomem *sgdma_base;
- void __iomem *core_base;
- struct sgdma_request *sgdma_request;
- dma_addr_t sgdma_request_pa;
-};
-
-static u8 sata_oxnas_check_status(struct ata_port *ap);
-static int sata_oxnas_cleanup(struct ata_host *ah);
-static void sata_oxnas_tf_load(struct ata_port *ap,
- const struct ata_taskfile *tf);
-static void sata_oxnas_irq_on(struct ata_port *ap);
-static void sata_oxnas_post_reset_init(struct ata_port *ap);
-
-static int sata_oxnas_acquire_hw(struct ata_port *ap, int may_sleep,
- int timeout_jiffies);
-static void sata_oxnas_release_hw(struct ata_port *ap);
-
-static const void *HW_LOCKER_UID = (void *)0xdeadbeef;
-
-/***************************************************************************
-* ASIC access
-***************************************************************************/
-static void wait_cr_ack(void __iomem *phy_base)
-{
- while ((ioread32(phy_base + PHY_STAT) >> 16) & 0x1f)
- ; /* wait for an ack bit to be set */
-}
-
-static u16 read_cr(void __iomem *phy_base, u16 address)
-{
- iowrite32((u32)address, phy_base + PHY_STAT);
- wait_cr_ack(phy_base);
- iowrite32(CR_READ_ENABLE, phy_base + PHY_DATA);
- wait_cr_ack(phy_base);
- return (u16)ioread32(phy_base + PHY_STAT);
-}
-
-static void write_cr(void __iomem *phy_base, u16 data, u16 address)
-{
- iowrite32((u32)address, phy_base + PHY_STAT);
- wait_cr_ack(phy_base);
- iowrite32((data | CR_CAP_DATA), phy_base + PHY_DATA);
- wait_cr_ack(phy_base);
- iowrite32(CR_WRITE_ENABLE, phy_base + PHY_DATA);
- wait_cr_ack(phy_base);
-}
-
-#define PH_GAIN 2
-#define FR_GAIN 3
-#define PH_GAIN_OFFSET 6
-#define FR_GAIN_OFFSET 8
-#define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
-#define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
-#define USE_INT_SETTING (1<<5)
-
-void workaround5458(struct ata_host *ah)
-{
- struct sata_oxnas_host_priv *hd = ah->private_data;
- void __iomem *phy_base = hd->phy_base;
- u16 rx_control;
- unsigned i;
-
- for (i = 0; i < 2; i++) {
- rx_control = read_cr(phy_base, 0x201d + (i << 8));
- rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
- rx_control |= PH_GAIN << PH_GAIN_OFFSET;
- rx_control |= (FR_GAIN << FR_GAIN_OFFSET) | USE_INT_SETTING;
- write_cr(phy_base, rx_control, 0x201d+(i<<8));
- }
-}
-
-/**
- * allows access to the link layer registers
- * @param link_reg the link layer register to access (oxsemi indexing ie
- * 00 = static config, 04 = phy ctrl)
- */
-void sata_oxnas_link_write(struct ata_port *ap, unsigned int link_reg, u32 val)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
- void __iomem *port_base = pd->port_base;
- u32 patience;
- unsigned long flags;
-
- DPRINTK("P%d [0x%02x]->0x%08x\n", ap->port_no, link_reg, val);
-
- spin_lock_irqsave(&hd->phy_lock, flags);
- iowrite32(val, port_base + LINK_DATA);
-
- /* accessed twice as a work around for a bug in the SATA abp bridge
- * hardware (bug 6828) */
- iowrite32(link_reg , port_base + LINK_WR_ADDR);
- ioread32(port_base + LINK_WR_ADDR);
-
- for (patience = 0x100000; patience > 0; --patience) {
- if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
- break;
- }
- spin_unlock_irqrestore(&hd->phy_lock, flags);
-}
-
-static int sata_oxnas_scr_write_port(struct ata_port *ap, unsigned int sc_reg,
- u32 val)
-{
- sata_oxnas_link_write(ap, 0x20 + (sc_reg * 4), val);
- return 0;
-}
-
-static int sata_oxnas_scr_write(struct ata_link *link, unsigned int sc_reg,
- u32 val)
-{
- return sata_oxnas_scr_write_port(link->ap, sc_reg, val);
-}
-
-u32 sata_oxnas_link_read(struct ata_port *ap, unsigned int link_reg)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
- void __iomem *port_base = pd->port_base;
- u32 result;
- u32 patience;
- unsigned long flags;
-
- spin_lock_irqsave(&hd->phy_lock, flags);
- /* accessed twice as a work around for a bug in the SATA abp bridge
- * hardware (bug 6828) */
- iowrite32(link_reg, port_base + LINK_RD_ADDR);
- ioread32(port_base + LINK_RD_ADDR);
-
- for (patience = 0x100000; patience > 0; --patience) {
- if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
- break;
- }
- if (patience == 0)
- DPRINTK("link read timed out for port %d\n", ap->port_no);
-
- result = ioread32(port_base + LINK_DATA);
- spin_unlock_irqrestore(&hd->phy_lock, flags);
-
- return result;
-}
-
-static int sata_oxnas_scr_read_port(struct ata_port *ap, unsigned int sc_reg,
- u32 *val)
-{
- *val = sata_oxnas_link_read(ap, 0x20 + (sc_reg*4));
- return 0;
-}
-
-static int sata_oxnas_scr_read(struct ata_link *link,
- unsigned int sc_reg, u32 *val)
-{
- return sata_oxnas_scr_read_port(link->ap, sc_reg, val);
-}
-
-/**
- * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
- * registered, to be sure hardware is quiet. It clears and masks interrupt bits
- * in the SATA core.
- *
- * @param ap hardware with the registers in
- */
-static void sata_oxnas_irq_clear(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *port_priv = ap->private_data;
-
- /* clear pending interrupts */
- iowrite32(~0, port_priv->port_base + INT_CLEAR);
- iowrite32(COREINT_END, port_priv->core_base + CORE_INT_CLEAR);
-}
-
-/**
- * qc_issue is used to make a command active, once the hardware and S/G tables
- * have been prepared. IDE BMDMA drivers use the helper function
- * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
- * drivers roll their own ->qc_issue implementation, using this as the
- * "issue new ATA command to hardware" hook.
- * @param qc the queued command to issue
- */
-static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd *qc)
-{
- struct sata_oxnas_port_priv *pd = qc->ap->private_data;
- struct sata_oxnas_host_priv *hd = qc->ap->host->private_data;
-
- void __iomem *port_base = pd->port_base;
- void __iomem *core_base = pd->core_base;
- int port_no = qc->ap->port_no;
- int no_microcode = (hd->current_ucode == UNKNOWN_MODE);
- u32 reg;
-
- /* check the core is idle */
- if (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY) {
- int count = 0;
-
- DPRINTK("core busy for a command on port %d\n",
- qc->ap->port_no);
- do {
- mdelay(1);
- if (++count > 100) {
- DPRINTK("core busy for a command on port %d\n",
- qc->ap->port_no);
- /* CrazyDumpDebug(); */
- sata_oxnas_cleanup(qc->ap->host);
- }
- } while (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY);
- }
-
- /* enable passing of error signals to DMA sub-core by clearing the
- * appropriate bit */
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- if (no_microcode)
- reg |= (DPC_ERROR_MASK_BIT | (DPC_ERROR_MASK_BIT << 1));
- reg &= ~(DPC_ERROR_MASK_BIT << port_no);
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
-
- /* Disable all interrupts for ports and RAID controller */
- iowrite32(~0, port_base + INT_DISABLE);
-
- /* Disable all interrupts for core */
- iowrite32(~0, core_base + CORE_INT_DISABLE);
- wmb();
-
- /* Load the command settings into the orb registers */
- sata_oxnas_tf_load(qc->ap, &qc->tf);
-
- /* both pio and dma commands use dma */
- if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
- /* Start the DMA */
- iowrite32(SGDMA_CONTROL_GO, pd->sgdma_base + SGDMA_CONTROL);
- wmb();
- }
-
- /* enable End of command interrupt */
- iowrite32(INT_WANT, port_base + INT_ENABLE);
- iowrite32(COREINT_END, core_base + CORE_INT_ENABLE);
- wmb();
-
- /* Start the command */
- reg = ioread32(port_base + SATA_COMMAND);
- reg &= ~SATA_OPCODE_MASK;
- reg |= CMD_WRITE_TO_ORB_REGS;
- iowrite32(reg , port_base + SATA_COMMAND);
- wmb();
-
- return 0;
-}
-
-/**
- * Will schedule the libATA error handler on the premise that there has
- * been a hotplug event on the port specified
- */
-void sata_oxnas_checkforhotplug(struct ata_port *ap)
-{
- DPRINTK("ENTER\n");
-
- ata_ehi_hotplugged(&ap->link.eh_info);
- ata_port_freeze(ap);
-}
-
-
-/**************************************************************************/
-/* Locking */
-/**************************************************************************/
-/**
- * The underlying function that controls access to the sata core
- *
- * @return non-zero indicates that you have acquired exclusive access to the
- * sata core.
- */
-static int __acquire_sata_core(
- struct ata_host *ah,
- int port_no,
- oxnas_sata_isr_callback_t callback,
- void *arg,
- int may_sleep,
- int timeout_jiffies,
- int hw_access,
- void *uid,
- int locker_type)
-{
- unsigned long end = jiffies + timeout_jiffies;
- int acquired = 0;
- unsigned long flags;
- int timed_out = 0;
- struct sata_oxnas_host_priv *hd;
-
- DEFINE_WAIT(wait);
-
- if (!ah)
- return acquired;
-
- hd = ah->private_data;
-
- spin_lock_irqsave(&hd->core_lock, flags);
-
- DPRINTK("Entered uid %p, port %d, h/w count %d, d count %d, "
- "callback %p, hw_access %d, core_locked %d, "
- "reentrant_port_no %d, isr_callback %p\n",
- uid, port_no, hd->hw_lock_count, hd->direct_lock_count,
- callback, hw_access, hd->core_locked, hd->reentrant_port_no,
- hd->isr_callback);
-
- while (!timed_out) {
- if (hd->core_locked ||
- (!hw_access && hd->scsi_nonblocking_attempts)) {
- /* Can only allow access if from SCSI/SATA stack and if
- * reentrant access is allowed and this access is to the
- * same port for which the lock is current held
- */
- if (hw_access && (port_no == hd->reentrant_port_no)) {
- BUG_ON(!hd->hw_lock_count);
- ++(hd->hw_lock_count);
-
- DPRINTK("Allow SCSI/SATA re-entrant access to "
- "uid %p port %d\n", uid, port_no);
- acquired = 1;
- break;
- } else if (!hw_access) {
- if ((locker_type == SATA_READER) &&
- (hd->current_locker_type == SATA_READER)) {
- WARN(1,
- "Already locked by reader, "
- "uid %p, locker_uid %p, "
- "port %d, h/w count %d, "
- "d count %d, hw_access %d\n",
- uid, hd->locker_uid, port_no,
- hd->hw_lock_count,
- hd->direct_lock_count,
- hw_access);
- goto check_uid;
- }
-
- if ((locker_type != SATA_READER) &&
- (locker_type != SATA_WRITER)) {
- goto wait_for_lock;
- }
-
-check_uid:
- WARN(uid == hd->locker_uid, "Attempt to lock "
- "by locker type %d uid %p, already "
- "locked by locker type %d with "
- "locker_uid %p, port %d, "
- "h/w count %d, d count %d, "
- "hw_access %d\n", locker_type, uid,
- hd->current_locker_type,
- hd->locker_uid, port_no,
- hd->hw_lock_count,
- hd->direct_lock_count, hw_access);
- }
- } else {
- WARN(hd->hw_lock_count || hd->direct_lock_count,
- "Core unlocked but counts non-zero: uid %p, "
- "locker_uid %p, port %d, h/w count %d, "
- "d count %d, hw_access %d\n", uid,
- hd->locker_uid, port_no, hd->hw_lock_count,
- hd->direct_lock_count, hw_access);
-
- BUG_ON(hd->current_locker_type != SATA_UNLOCKED);
-
- WARN(hd->locker_uid, "Attempt to lock uid %p when "
- "locker_uid %p is non-zero, port %d, "
- "h/w count %d, d count %d, hw_access %d\n",
- uid, hd->locker_uid, port_no, hd->hw_lock_count,
- hd->direct_lock_count, hw_access);
-
- if (!hw_access) {
- /* Direct access attempting to acquire
- * non-contented lock
- */
- /* Must have callback for direct access */
- BUG_ON(!callback);
- /* Sanity check lock state */
- BUG_ON(hd->reentrant_port_no != -1);
-
- hd->isr_callback = callback;
- hd->isr_arg = arg;
- ++(hd->direct_lock_count);
-
- hd->current_locker_type = locker_type;
- } else {
- /* SCSI/SATA attempting to acquire
- * non-contented lock
- */
- /* No callbacks for SCSI/SATA access */
- BUG_ON(callback);
- /* No callback args for SCSI/SATA access */
- BUG_ON(arg);
-
- /* Sanity check lock state */
- BUG_ON(hd->isr_callback);
- BUG_ON(hd->isr_arg);
-
- ++(hd->hw_lock_count);
- hd->reentrant_port_no = port_no;
-
- hd->current_locker_type = SATA_SCSI_STACK;
- }
-
- hd->core_locked = 1;
- hd->locker_uid = uid;
- acquired = 1;
- break;
- }
-
-wait_for_lock:
- if (!may_sleep) {
- DPRINTK("Denying for uid %p locker_type %d, "
- "hw_access %d, port %d, current_locker_type %d as "
- "cannot sleep\n", uid, locker_type, hw_access, port_no,
- hd->current_locker_type);
-
- if (hw_access)
- ++(hd->scsi_nonblocking_attempts);
-
- break;
- }
-
- /* Core is locked and we're allowed to sleep, so wait to be
- * awoken when the core is unlocked
- */
- for (;;) {
- prepare_to_wait(hw_access ? &hd->scsi_wait_queue :
- &hd->fast_wait_queue,
- &wait, TASK_UNINTERRUPTIBLE);
- if (!hd->core_locked &&
- !(!hw_access && hd->scsi_nonblocking_attempts)) {
- /* We're going to use variables that will have
- * been changed by the waker prior to clearing
- * core_locked so we need to ensure we see
- * changes to all those variables
- */
- smp_rmb();
- break;
- }
- if (time_after(jiffies, end)) {
- printk(KERN_WARNING "__acquire_sata_core() "
- "uid %p failing for port %d timed out, "
- "locker_uid %p, h/w count %d, "
- "d count %d, callback %p, hw_access %d, "
- "core_locked %d, reentrant_port_no %d, "
- "isr_callback %p, isr_arg %p\n", uid,
- port_no, hd->locker_uid,
- hd->hw_lock_count,
- hd->direct_lock_count, callback,
- hw_access, hd->core_locked,
- hd->reentrant_port_no, hd->isr_callback,
- hd->isr_arg);
- timed_out = 1;
- break;
- }
- spin_unlock_irqrestore(&hd->core_lock, flags);
- if (!schedule_timeout(4*HZ)) {
- printk(KERN_INFO "__acquire_sata_core() uid %p, "
- "locker_uid %p, timed-out of "
- "schedule(), checking overall timeout\n",
- uid, hd->locker_uid);
- }
- spin_lock_irqsave(&hd->core_lock, flags);
- }
- finish_wait(hw_access ? &hd->scsi_wait_queue :
- &hd->fast_wait_queue, &wait);
- }
-
- if (hw_access && acquired) {
- if (hd->scsi_nonblocking_attempts)
- hd->scsi_nonblocking_attempts = 0;
-
- /* Wake any other SCSI/SATA waiters so they can get reentrant
- * access to the same port if appropriate. This is because if
- * the SATA core is locked by fast access, or SCSI/SATA access
- * to other port, then can have >1 SCSI/SATA waiters on the wait
- * list so want to give reentrant accessors a chance to get
- * access ASAP
- */
- if (!list_empty(&hd->scsi_wait_queue.head))
- wake_up(&hd->scsi_wait_queue);
- }
-
- DPRINTK("Leaving uid %p with acquired = %d, port %d, callback %p\n",
- uid, acquired, port_no, callback);
-
- spin_unlock_irqrestore(&hd->core_lock, flags);
-
- return acquired;
-}
-
-int sata_core_has_fast_waiters(struct ata_host *ah)
-{
- int has_waiters;
- unsigned long flags;
- struct sata_oxnas_host_priv *hd = ah->private_data;
-
- spin_lock_irqsave(&hd->core_lock, flags);
- has_waiters = !list_empty(&hd->fast_wait_queue.head);
- spin_unlock_irqrestore(&hd->core_lock, flags);
-
- return has_waiters;
-}
-EXPORT_SYMBOL(sata_core_has_fast_waiters);
-
-int sata_core_has_scsi_waiters(struct ata_host *ah)
-{
- int has_waiters;
- unsigned long flags;
- struct sata_oxnas_host_priv *hd = ah->private_data;
-
- spin_lock_irqsave(&hd->core_lock, flags);
- has_waiters = hd->scsi_nonblocking_attempts ||
- !list_empty(&hd->scsi_wait_queue.head);
- spin_unlock_irqrestore(&hd->core_lock, flags);
-
- return has_waiters;
-}
-EXPORT_SYMBOL(sata_core_has_scsi_waiters);
-
-/*
- * ata_port operation to gain ownership of the SATA hardware prior to issuing
- * a command against a SATA host. Allows any number of users of the port against
- * which the lock was first acquired, thus enforcing that only one SATA core
- * port may be operated on at once.
- */
-static int sata_oxnas_acquire_hw(
- struct ata_port *ap,
- int may_sleep,
- int timeout_jiffies)
-{
- return __acquire_sata_core(ap->host, ap->port_no, NULL, 0, may_sleep,
- timeout_jiffies, 1, (void *)HW_LOCKER_UID,
- SATA_SCSI_STACK);
-}
-
-/*
- * operation to release ownership of the SATA hardware
- */
-static void sata_oxnas_release_hw(struct ata_port *ap)
-{
- unsigned long flags;
- int released = 0;
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- spin_lock_irqsave(&hd->core_lock, flags);
-
- DPRINTK("Entered port_no = %d, h/w count %d, d count %d, "
- "core locked = %d, reentrant_port_no = %d, isr_callback %p\n",
- ap->port_no, hd->hw_lock_count, hd->direct_lock_count,
- hd->core_locked, hd->reentrant_port_no, hd->isr_callback);
-
- if (!hd->core_locked) {
- /* Nobody holds the SATA lock */
- printk(KERN_WARNING "Nobody holds SATA lock, port_no %d\n",
- ap->port_no);
- released = 1;
- } else if (!hd->hw_lock_count) {
- /* SCSI/SATA has released without holding the lock */
- printk(KERN_WARNING "SCSI/SATA does not hold SATA lock, "
- "port_no %d\n", ap->port_no);
- } else {
- /* Trap incorrect usage */
- BUG_ON(hd->reentrant_port_no == -1);
- BUG_ON(ap->port_no != hd->reentrant_port_no);
- BUG_ON(hd->direct_lock_count);
- BUG_ON(hd->current_locker_type != SATA_SCSI_STACK);
-
- WARN(!hd->locker_uid || (hd->locker_uid != HW_LOCKER_UID),
- "Invalid locker uid %p, h/w count %d, d count %d, "
- "reentrant_port_no %d, core_locked %d, "
- "isr_callback %p\n", hd->locker_uid, hd->hw_lock_count,
- hd->direct_lock_count, hd->reentrant_port_no,
- hd->core_locked, hd->isr_callback);
-
- if (--(hd->hw_lock_count)) {
- DPRINTK("Still nested port_no %d\n", ap->port_no);
- } else {
- DPRINTK("Release port_no %d\n", ap->port_no);
- hd->reentrant_port_no = -1;
- hd->isr_callback = NULL;
- hd->current_locker_type = SATA_UNLOCKED;
- hd->locker_uid = 0;
- hd->core_locked = 0;
- released = 1;
- wake_up(!list_empty(&hd->scsi_wait_queue.head) ?
- &hd->scsi_wait_queue :
- &hd->fast_wait_queue);
- }
- }
-
- DPRINTK("Leaving, port_no %d, count %d\n", ap->port_no,
- hd->hw_lock_count);
-
- spin_unlock_irqrestore(&hd->core_lock, flags);
-
- /* CONFIG_SATA_OX820_DIRECT_HWRAID */
- /* if (released)
- ox820hwraid_restart_queue();
- } */
-}
-
-static inline int sata_oxnas_is_host_frozen(struct ata_host *ah)
-{
- struct sata_oxnas_host_priv *hd = ah->private_data;
-
- smp_rmb();
- return hd->port_in_eh || hd->port_frozen;
-}
-
-
-static inline u32 sata_oxnas_hostportbusy(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- return (ioread32(hd->port_base + SATA_COMMAND) & CMD_CORE_BUSY) ||
- (hd->n_ports > 1 &&
- (ioread32(hd->port_base + PORT_SIZE + SATA_COMMAND) &
- CMD_CORE_BUSY));
-}
-
-static inline u32 sata_oxnas_hostdmabusy(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
-
- return ioread32(pd->sgdma_base + SGDMA_STATUS) & SGDMA_BUSY;
-}
-
-
-/**
- * Turns on the cores clock and resets it
- */
-static void sata_oxnas_reset_core(struct ata_host *ah)
-{
- struct sata_oxnas_host_priv *host_priv = ah->private_data;
- int n;
-
- DPRINTK("ENTER\n");
- clk_prepare_enable(host_priv->clk);
-
- reset_control_assert(host_priv->rst_sata);
- reset_control_assert(host_priv->rst_link);
- reset_control_assert(host_priv->rst_phy);
-
- udelay(50);
-
- /* un-reset the PHY, then Link and Controller */
- reset_control_deassert(host_priv->rst_phy);
- udelay(50);
-
- reset_control_deassert(host_priv->rst_sata);
- reset_control_deassert(host_priv->rst_link);
- udelay(50);
-
- workaround5458(ah);
- /* tune for sata compatibility */
- sata_oxnas_link_write(ah->ports[0], 0x60, 0x2988);
-
- for (n = 0; n < host_priv->n_ports; n++) {
- /* each port in turn */
- sata_oxnas_link_write(ah->ports[n], 0x70, 0x55629);
- }
- udelay(50);
-}
-
-
-/**
- * Called after an identify device command has worked out what kind of device
- * is on the port
- *
- * @param port The port to configure
- * @param pdev The hardware associated with controlling the port
- */
-static void sata_oxnas_dev_config(struct ata_device *pdev)
-{
- struct sata_oxnas_port_priv *pd = pdev->link->ap->private_data;
- void __iomem *port_base = pd->port_base;
- u32 reg;
-
- DPRINTK("ENTER\n");
- /* Set the bits to put the port into 28 or 48-bit node */
- reg = ioread32(port_base + DRIVE_CONTROL);
- reg &= ~3;
- reg |= (pdev->flags & ATA_DFLAG_LBA48) ? DR_CON_48 : DR_CON_28;
- iowrite32(reg, port_base + DRIVE_CONTROL);
-
- /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
- if (pdev->flags & ATA_DFLAG_LBA48) {
- reg = ioread32(port_base + PORT_CONTROL);
- reg |= 2;
- iowrite32(reg, port_base + PORT_CONTROL);
- }
-}
-/**
- * called to write a taskfile into the ORB registers
- * @param ap hardware with the registers in
- * @param tf taskfile to write to the registers
- */
-static void sata_oxnas_tf_load(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- u32 count = 0;
- u32 Orb1 = 0;
- u32 Orb2 = 0;
- u32 Orb3 = 0;
- u32 Orb4 = 0;
- u32 Command_Reg;
-
- struct sata_oxnas_port_priv *port_priv = ap->private_data;
- void __iomem *port_base = port_priv->port_base;
- unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
-
- /* wait a maximum of 10ms for the core to be idle */
- do {
- Command_Reg = ioread32(port_base + SATA_COMMAND);
- if (!(Command_Reg & CMD_CORE_BUSY))
- break;
- count++;
- udelay(50);
- } while (count < 200);
-
- /* check if the ctl register has interrupts disabled or enabled and
- * modify the interrupt enable registers on the ata core as required */
- if (tf->ctl & ATA_NIEN) {
- /* interrupts disabled */
- u32 mask = (COREINT_END << ap->port_no);
-
- iowrite32(mask, port_priv->core_base + CORE_INT_DISABLE);
- sata_oxnas_irq_clear(ap);
- } else {
- sata_oxnas_irq_on(ap);
- }
-
- Orb2 |= (tf->command) << 24;
-
- /* write 48 or 28 bit tf parameters */
- if (is_addr) {
- /* set LBA bit as it's an address */
- Orb1 |= (tf->device & ATA_LBA) << 24;
-
- if (tf->flags & ATA_TFLAG_LBA48) {
- Orb1 |= ATA_LBA << 24;
- Orb2 |= (tf->hob_nsect) << 8;
- Orb3 |= (tf->hob_lbal) << 24;
- Orb4 |= (tf->hob_lbam) << 0;
- Orb4 |= (tf->hob_lbah) << 8;
- Orb4 |= (tf->hob_feature) << 16;
- } else {
- Orb3 |= (tf->device & 0xf) << 24;
- }
-
- /* write 28-bit lba */
- Orb2 |= (tf->nsect) << 0;
- Orb2 |= (tf->feature) << 16;
- Orb3 |= (tf->lbal) << 0;
- Orb3 |= (tf->lbam) << 8;
- Orb3 |= (tf->lbah) << 16;
- Orb4 |= (tf->ctl) << 24;
- }
-
- if (tf->flags & ATA_TFLAG_DEVICE)
- Orb1 |= (tf->device) << 24;
-
- ap->last_ctl = tf->ctl;
-
- /* write values to registers */
- iowrite32(Orb1, port_base + ORB1);
- iowrite32(Orb2, port_base + ORB2);
- iowrite32(Orb3, port_base + ORB3);
- iowrite32(Orb4, port_base + ORB4);
-}
-
-
-void sata_oxnas_set_mode(struct ata_host *ah, u32 mode, u32 force)
-{
- struct sata_oxnas_host_priv *host_priv = ah->private_data;
- void __iomem *core_base = host_priv->core_base;
-
- unsigned int *src;
- void __iomem *dst;
- unsigned int progmicrocode = 0;
- unsigned int changeparameters = 0;
-
- u32 previous_mode;
-
- /* these micro-code programs _should_ include the version word */
-
- /* JBOD */
- static const unsigned int jbod[] = {
- 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
- 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
- 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
- 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
- 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
- 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
- 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
- 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
- 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
- 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
- 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
- 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
- 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
- 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
- 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
- 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
- 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
- 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
- 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
- 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
- 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
- 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
- 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
- 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
- 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
- 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
- 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
- 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
- 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
- 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
- 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
- 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
- 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
- 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
- 0x00718908, 0x0208A206, 0x00EE0005, ~0
- };
-
- /* Bi-Modal RAID-0/1 */
- static const unsigned int raid[] = {
- 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
- 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
- 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
- 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
- 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
- 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
- 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
- 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
- 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
- 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
- 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
- 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
- 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
- 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
- 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
- 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
- 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
- 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
- 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
- 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
- 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
- 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
- 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
- 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
- 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
- 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
- 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
- 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
- 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
- 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
- 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
- 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
- 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
- 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
- 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
- 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
- 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
- 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
- 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
- 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
- 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
- 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
- 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
- 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
- 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
- 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
- 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
- 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
- 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
- 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
- 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
- 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
- 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
- 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
- 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
- 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
- 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
- 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
- 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
- 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
- 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
- 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
- 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
- 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
- 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
- 0x02400000, ~0
- };
-
- DPRINTK("ENTER: mode:%d, force:%d\n", mode, force);
-
- if (force)
- previous_mode = UNKNOWN_MODE;
- else
- previous_mode = host_priv->current_ucode;
-
- if (mode == previous_mode)
- return;
-
- host_priv->current_ucode = mode;
-
- /* decide what needs to be done using the STD in my logbook */
- switch (previous_mode) {
- case OXNASSATA_RAID1:
- switch (mode) {
- case OXNASSATA_RAID0:
- changeparameters = 1;
- break;
- case OXNASSATA_NOTRAID:
- changeparameters = 1;
- progmicrocode = 1;
- break;
- }
- break;
- case OXNASSATA_RAID0:
- switch (mode) {
- case OXNASSATA_RAID1:
- changeparameters = 1;
- break;
- case OXNASSATA_NOTRAID:
- changeparameters = 1;
- progmicrocode = 1;
- break;
- }
- break;
- case OXNASSATA_NOTRAID:
- switch (mode) {
- case OXNASSATA_RAID0:
- case OXNASSATA_RAID1:
- changeparameters = 1;
- progmicrocode = 1;
- break;
- }
- break;
- case UNKNOWN_MODE:
- changeparameters = 1;
- progmicrocode = 1;
- break;
- }
-
- /* no need to reprogram everything if already in the right mode */
- if (progmicrocode) {
- /* reset micro-code processor */
- iowrite32(1, core_base + PROC_RESET);
- wmb();
-
- /* select micro-code */
- switch (mode) {
- case OXNASSATA_RAID1:
- case OXNASSATA_RAID0:
- VPRINTK("Loading RAID micro-code\n");
- src = (unsigned int *)&raid[1];
- break;
- case OXNASSATA_NOTRAID:
- VPRINTK("Loading JBOD micro-code\n");
- src = (unsigned int *)&jbod[1];
- break;
- default:
- BUG();
- break;
- }
-
- /* load micro code */
- dst = core_base + UCODE_STORE;
- while (*src != ~0) {
- iowrite32(*src, dst);
- src++;
- dst += sizeof(*src);
- }
- wmb();
- }
-
- if (changeparameters) {
- u32 reg;
- /* set other mode dependent flags */
- switch (mode) {
- case OXNASSATA_RAID1:
- /* clear JBOD mode */
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- reg |= DPC_JBOD_UCODE;
- reg &= ~DPC_FIS_SWCH;
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
- wmb();
-
- /* set the hardware up for RAID-1 */
- iowrite32(0, core_base + RAID_WP_BOT_LOW);
- iowrite32(0, core_base + RAID_WP_BOT_HIGH);
- iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
- iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
- iowrite32(0, core_base + RAID_SIZE_LOW);
- iowrite32(0, core_base + RAID_SIZE_HIGH);
- wmb();
- break;
- case OXNASSATA_RAID0:
- /* clear JBOD mode */
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- reg |= DPC_JBOD_UCODE;
- reg &= ~DPC_FIS_SWCH;
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
- wmb();
-
- /* set the hardware up for RAID-1 */
- iowrite32(0, core_base + RAID_WP_BOT_LOW);
- iowrite32(0, core_base + RAID_WP_BOT_HIGH);
- iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
- iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
- iowrite32(0xffffffff, core_base + RAID_SIZE_LOW);
- iowrite32(0x7fffffff, core_base + RAID_SIZE_HIGH);
- wmb();
- break;
- case OXNASSATA_NOTRAID:
- /* enable jbod mode */
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- reg &= ~DPC_JBOD_UCODE;
- reg &= ~DPC_FIS_SWCH;
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
- wmb();
-
- /* start micro-code processor*/
- iowrite32(1, core_base + PROC_START);
- break;
- default:
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- reg |= DPC_JBOD_UCODE;
- reg &= ~DPC_FIS_SWCH;
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
- wmb();
- break;
- }
- }
-}
-
-/**
- * sends a sync-escape if there is a link present
- */
-static inline void sata_oxnas_send_sync_escape(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 reg;
-
- /* read the SSTATUS register and only send a sync escape if there is a
- * link active */
- if ((sata_oxnas_link_read(ap, 0x20) & 3) == 3) {
- reg = ioread32(pd->port_base + SATA_COMMAND);
- reg &= ~SATA_OPCODE_MASK;
- reg |= CMD_SYNC_ESCAPE;
- iowrite32(reg, pd->port_base + SATA_COMMAND);
- }
-}
-
-/* clears errors */
-static inline void sata_oxnas_clear_CS_error(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 *base = pd->port_base;
- u32 reg;
-
- reg = ioread32(base + SATA_CONTROL);
- reg &= SATA_CTL_ERR_MASK;
- iowrite32(reg, base + SATA_CONTROL);
-}
-
-static inline void sata_oxnas_reset_sgdma(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
-
- iowrite32(SGDMA_RESETS_CTRL, pd->sgdma_base + SGDMA_RESETS);
-}
-
-static inline void sata_oxnas_reset_dma(struct ata_port *ap, int assert)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 reg;
-
- reg = ioread32(pd->dmactl_base + DMA_CONTROL);
- if (assert)
- reg |= DMA_CONTROL_RESET;
- else
- reg &= ~DMA_CONTROL_RESET;
-
- iowrite32(reg, pd->dmactl_base + DMA_CONTROL);
-};
-
-/**
- * Clears the error caused by the core's registers being accessed when the
- * core is busy.
- */
-static inline void sata_oxnas_clear_reg_access_error(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 *base = pd->port_base;
- u32 reg;
-
- reg = ioread32(base + INT_STATUS);
-
- DPRINTK("ENTER\n");
- if (reg & INT_REG_ACCESS_ERR) {
- DPRINTK("clearing register access error on port %d\n",
- ap->port_no);
- iowrite32(INT_REG_ACCESS_ERR, base + INT_STATUS);
- }
- reg = ioread32(base + INT_STATUS);
- if (reg & INT_REG_ACCESS_ERR)
- DPRINTK("register access error didn't clear\n");
-}
-
-static inline void sata_oxnas_clear_sctl_error(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 *base = pd->port_base;
- u32 reg;
-
- reg = ioread32(base + SATA_CONTROL);
- reg |= SCTL_CLR_ERR;
- iowrite32(reg, base + SATA_CONTROL);
-}
-
-static inline void sata_oxnas_clear_raid_error(struct ata_host *ah)
-{
- return;
-};
-
-/**
- * Clean up all the state machines in the sata core.
- * @return post cleanup action required
- */
-static int sata_oxnas_cleanup(struct ata_host *ah)
-{
- struct sata_oxnas_host_priv *hd = ah->private_data;
- int actions_required = 0;
- int n;
-
- printk(KERN_INFO "sata_oxnas: resetting SATA core\n");
- /* core not recovering, reset it */
- mdelay(5);
- sata_oxnas_reset_core(ah);
- mdelay(5);
- actions_required |= OXNAS_SATA_REINIT;
- /* Perform any SATA core re-initialisation after reset post reset init
- * needs to be called for both ports as there's one reset for both
- * ports */
- for (n = 0; n < hd->n_ports; n++)
- sata_oxnas_post_reset_init(ah->ports[n]);
-
-
- return actions_required;
-}
-
-/**
- * ata_qc_new - Request an available ATA command, for queueing
- * @ap: Port associated with device @dev
- * @return non zero will refuse a new command, zero will may grant on subject
- * to conditions elsewhere.
- *
- */
-static int sata_oxnas_qc_new(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("port %d\n", ap->port_no);
- smp_rmb();
- if (hd->port_frozen || hd->port_in_eh)
- return 1;
- else
- return !sata_oxnas_acquire_hw(ap, 0, 0);
-}
-
-/**
- * releases the lock on the port the command used
- */
-static void sata_oxnas_qc_free(struct ata_queued_cmd *qc)
-{
- DPRINTK("\n");
- sata_oxnas_release_hw(qc->ap);
-}
-
-static void sata_oxnas_freeze(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("\n");
- hd->port_frozen |= BIT(ap->port_no);
- smp_wmb();
-}
-
-static void sata_oxnas_thaw(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("\n");
- hd->port_frozen &= ~BIT(ap->port_no);
- smp_wmb();
-}
-
-void sata_oxnas_freeze_host(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("ENTER\n");
- hd->port_in_eh |= BIT(ap->port_no);
- smp_wmb();
-}
-
-void sata_oxnas_thaw_host(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("ENTER\n");
- hd->port_in_eh &= ~BIT(ap->port_no);
- smp_wmb();
-}
-
-static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd *qc)
-{
- DPRINTK("ENTER\n");
- /* If the core is busy here, make it idle */
- if (qc->flags & ATA_QCFLAG_FAILED)
- sata_oxnas_cleanup(qc->ap->host);
-}
-
-
-/**
- * turn on the interrupts
- *
- * @param ap Hardware with the registers in
- */
-static void sata_oxnas_irq_on(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 mask = (COREINT_END << ap->port_no);
-
- /* Clear pending interrupts */
- iowrite32(~0, pd->port_base + INT_CLEAR);
- iowrite32(mask, pd->core_base + CORE_INT_STATUS);
- wmb();
-
- /* enable End of command interrupt */
- iowrite32(INT_WANT, pd->port_base + INT_ENABLE);
- iowrite32(mask, pd->core_base + CORE_INT_ENABLE);
-}
-
-
-/** @return true if the port has a cable connected */
-int sata_oxnas_check_link(struct ata_port *ap)
-{
- int reg;
-
- sata_oxnas_scr_read_port(ap, SCR_STATUS, ®);
- /* Check for the cable present indicated by SCR status bit-0 set */
- return reg & 0x1;
-}
-
-/**
- * ata_std_postreset - standard postreset callback
- * @link: the target ata_link
- * @classes: classes of attached devices
- *
- * This function is invoked after a successful reset. Note that
- * the device might have been reset more than once using
- * different reset methods before postreset is invoked.
- *
- * LOCKING:
- * Kernel thread context (may sleep)
- */
-static void sata_oxnas_postreset(struct ata_link *link, unsigned int *classes)
-{
- struct ata_port *ap = link->ap;
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- unsigned int dev;
-
- DPRINTK("ENTER\n");
- ata_std_postreset(link, classes);
-
- /* turn on phy error detection by removing the masks */
- sata_oxnas_link_write(ap->host->ports[0], 0x0c, 0x30003);
- if (hd->n_ports > 1)
- sata_oxnas_link_write(ap->host->ports[1], 0x0c, 0x30003);
-
- /* bail out if no device is present */
- if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
- DPRINTK("EXIT, no device\n");
- return;
- }
-
- /* go through all the devices and configure them */
- for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
- if (ap->link.device[dev].class == ATA_DEV_ATA)
- sata_oxnas_dev_config(&(ap->link.device[dev]));
- }
-
- DPRINTK("EXIT\n");
-}
-
-/**
- * Called to read the hardware registers / DMA buffers, to
- * obtain the current set of taskfile register values.
- * @param ap hardware with the registers in
- * @param tf taskfile to read the registers into
- */
-static void sata_oxnas_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
-{
- struct sata_oxnas_port_priv *port_priv = ap->private_data;
- void __iomem *port_base = port_priv->port_base;
- /* read the orb registers */
- u32 Orb1 = ioread32(port_base + ORB1);
- u32 Orb2 = ioread32(port_base + ORB2);
- u32 Orb3 = ioread32(port_base + ORB3);
- u32 Orb4 = ioread32(port_base + ORB4);
-
- /* read common 28/48 bit tf parameters */
- tf->device = (Orb1 >> 24);
- tf->nsect = (Orb2 >> 0);
- tf->feature = (Orb2 >> 16);
- tf->command = sata_oxnas_check_status(ap);
-
- /* read 48 or 28 bit tf parameters */
- if (tf->flags & ATA_TFLAG_LBA48) {
- tf->hob_nsect = (Orb2 >> 8);
- tf->lbal = (Orb3 >> 0);
- tf->lbam = (Orb3 >> 8);
- tf->lbah = (Orb3 >> 16);
- tf->hob_lbal = (Orb3 >> 24);
- tf->hob_lbam = (Orb4 >> 0);
- tf->hob_lbah = (Orb4 >> 8);
- /* feature ext and control are write only */
- } else {
- /* read 28-bit lba */
- tf->lbal = (Orb3 >> 0);
- tf->lbam = (Orb3 >> 8);
- tf->lbah = (Orb3 >> 16);
- }
-}
-
-/**
- * Read a result task-file from the sata core registers.
- */
-static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd *qc)
-{
- /* Read the most recently received FIS from the SATA core ORB registers
- and convert to an ATA taskfile */
- sata_oxnas_tf_read(qc->ap, &qc->result_tf);
- return true;
-}
-
-/**
- * Reads the Status ATA shadow register from hardware.
- *
- * @return The status register
- */
-static u8 sata_oxnas_check_status(struct ata_port *ap)
-{
- u32 Reg;
- u8 status;
- struct sata_oxnas_port_priv *port_priv = ap->private_data;
- void __iomem *port_base = port_priv->port_base;
-
- /* read byte 3 of Orb2 register */
- status = ioread32(port_base + ORB2) >> 24;
-
- /* check for the drive going missing indicated by SCR status bits
- * 0-3 = 0 */
- sata_oxnas_scr_read_port(ap, SCR_STATUS, &Reg);
-
- if (!(Reg & 0x1)) {
- status |= ATA_DF;
- status |= ATA_ERR;
- }
-
- return status;
-}
-
-static inline void sata_oxnas_reset_ucode(struct ata_host *ah, int force,
- int no_microcode)
-{
- struct sata_oxnas_host_priv *hd = ah->private_data;
-
- DPRINTK("ENTER\n");
- if (no_microcode) {
- u32 reg;
-
- sata_oxnas_set_mode(ah, UNKNOWN_MODE, force);
- reg = ioread32(hd->core_base + DEVICE_CONTROL);
- reg |= DEVICE_CONTROL_ATA_ERR_OVERRIDE;
- iowrite32(reg, hd->core_base + DEVICE_CONTROL);
- } else {
- /* JBOD uCode */
- sata_oxnas_set_mode(ah, OXNASSATA_NOTRAID, force);
- /* Turn the work around off as it may have been left on by any
- * HW-RAID code that we've been working with */
- iowrite32(0x0, hd->core_base + PORT_ERROR_MASK);
- }
-}
-
-/**
- * Prepare as much as possible for a command without involving anything that is
- * shared between ports.
- */
-static enum ata_completion_errors sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
-{
- struct sata_oxnas_port_priv *pd;
- int port_no = qc->ap->port_no;
-
- /* if the port's not connected, complete now with an error */
- if (!sata_oxnas_check_link(qc->ap)) {
- ata_port_err(qc->ap,
- "port %d not connected completing with error\n",
- port_no);
- qc->err_mask |= AC_ERR_ATA_BUS;
- ata_qc_complete(qc);
- }
-
- sata_oxnas_reset_ucode(qc->ap->host, 0, 0);
-
- /* both pio and dma commands use dma */
- if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
-
- /* program the scatterlist into the prd table */
- ata_bmdma_qc_prep(qc);
-
- /* point the sgdma controller at the dma request structure */
- pd = qc->ap->private_data;
-
- iowrite32(pd->sgdma_request_pa,
- pd->sgdma_base + SGDMA_REQUESTPTR);
-
- /* setup the request table */
- if (port_no == 0) {
- pd->sgdma_request->control =
- (qc->dma_dir == DMA_FROM_DEVICE) ?
- SGDMA_REQCTL0IN : SGDMA_REQCTL0OUT;
- } else {
- pd->sgdma_request->control =
- (qc->dma_dir == DMA_FROM_DEVICE) ?
- SGDMA_REQCTL1IN : SGDMA_REQCTL1OUT;
- }
- pd->sgdma_request->qualifier = SGDMA_REQQUAL;
- pd->sgdma_request->src_pa = qc->ap->bmdma_prd_dma;
- pd->sgdma_request->dst_pa = qc->ap->bmdma_prd_dma;
- smp_wmb();
-
- /* tell it to wait */
- iowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL);
- }
-
- return AC_ERR_OK;
-}
-
-static int sata_oxnas_port_start(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
- struct device *dev = ap->host->dev;
- struct sata_oxnas_port_priv *pp;
- void *mem;
- dma_addr_t mem_dma;
-
- DPRINTK("ENTER\n");
-
- pp = kzalloc(sizeof(*pp), GFP_KERNEL);
- if (!pp)
- return -ENOMEM;
-
- pp->port_base = host_priv->port_base +
- (ap->port_no ? PORT_SIZE : 0);
- pp->dmactl_base = host_priv->dmactl_base +
- (ap->port_no ? DMA_CORESIZE : 0);
- pp->sgdma_base = host_priv->sgdma_base +
- (ap->port_no ? SGDMA_CORESIZE : 0);
- pp->core_base = host_priv->core_base;
-
- /* preallocated */
- if (host_priv->dma_size >= SATA_OXNAS_DMA_SIZE * host_priv->n_ports) {
- DPRINTK("using preallocated DMA\n");
- mem_dma = host_priv->dma_base +
- (ap->port_no ? SATA_OXNAS_DMA_SIZE : 0);
- mem = ioremap(mem_dma, SATA_OXNAS_DMA_SIZE);
- } else {
- mem = dma_alloc_coherent(dev, SATA_OXNAS_DMA_SIZE, &mem_dma,
- GFP_KERNEL);
- }
- if (!mem)
- goto err_ret;
-
- pp->sgdma_request_pa = mem_dma;
- pp->sgdma_request = mem;
-
- ap->bmdma_prd_dma = mem_dma + sizeof(struct sgdma_request);
- ap->bmdma_prd = mem + sizeof(struct sgdma_request);
-
- ap->private_data = pp;
-
- sata_oxnas_post_reset_init(ap);
-
- return 0;
-
-err_ret:
- kfree(pp);
- return -ENOMEM;
-
-}
-
-static void sata_oxnas_port_stop(struct ata_port *ap)
-{
- struct device *dev = ap->host->dev;
- struct sata_oxnas_port_priv *pp = ap->private_data;
- struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
-
- DPRINTK("ENTER\n");
- ap->private_data = NULL;
- if (host_priv->dma_size) {
- iounmap(pp->sgdma_request);
- } else {
- dma_free_coherent(dev, SATA_OXNAS_DMA_SIZE,
- pp->sgdma_request, pp->sgdma_request_pa);
- }
-
- kfree(pp);
-}
-
-
-static void sata_oxnas_post_reset_init(struct ata_port *ap)
-{
- uint dev;
-
- /* force to load u-code only once after reset */
- sata_oxnas_reset_ucode(ap->host, !ap->port_no, 0);
-
- /* turn on phy error detection by removing the masks */
- sata_oxnas_link_write(ap, 0x0C, 0x30003);
-
- /* enable hotplug event detection */
- sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
- sata_oxnas_scr_write_port(ap, SERROR_IRQ_MASK, 0x03feffff);
- sata_oxnas_scr_write_port(ap, SCR_ACTIVE, ~0 & ~(1 << 26) & ~(1 << 16));
-
- /* enable interrupts for ports */
- sata_oxnas_irq_on(ap);
-
- /* go through all the devices and configure them */
- for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
- if (ap->link.device[dev].class == ATA_DEV_ATA) {
- sata_std_hardreset(&ap->link, NULL, jiffies + HZ);
- sata_oxnas_dev_config(&(ap->link.device[dev]));
- }
- }
-
- /* clean up any remaining errors */
- sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
- VPRINTK("done\n");
-}
-
-/**
- * host_stop() is called when the rmmod or hot unplug process begins. The
- * hook must stop all hardware interrupts, DMA engines, etc.
- *
- * @param ap hardware with the registers in
- */
-static void sata_oxnas_host_stop(struct ata_host *host_set)
-{
- DPRINTK("\n");
-}
-
-
-#define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
-static void sata_oxnas_error_handler(struct ata_port *ap)
-{
- DPRINTK("Enter port_no %d\n", ap->port_no);
- sata_oxnas_freeze_host(ap);
-
- /* If the core is busy here, make it idle */
- sata_oxnas_cleanup(ap->host);
-
- ata_std_error_handler(ap);
-
- sata_oxnas_thaw_host(ap);
-}
-
-static int sata_oxnas_softreset(struct ata_link *link, unsigned int *class,
- unsigned long deadline)
-{
- struct ata_port *ap = link->ap;
- struct sata_oxnas_port_priv *pd = ap->private_data;
- void __iomem *port_base = pd->port_base;
- int rc;
-
- struct ata_taskfile tf;
- u32 Command_Reg;
-
- DPRINTK("ENTER\n");
-
- port_base = pd->port_base;
-
- if (ata_link_offline(link)) {
- DPRINTK("PHY reports no device\n");
- *class = ATA_DEV_NONE;
- goto out;
- }
-
- /* write value to register */
- iowrite32(0, port_base + ORB1);
- iowrite32(0, port_base + ORB2);
- iowrite32(0, port_base + ORB3);
- iowrite32((ap->ctl) << 24, port_base + ORB4);
-
- /* command the core to send a control FIS */
- Command_Reg = ioread32(port_base + SATA_COMMAND);
- Command_Reg &= ~SATA_OPCODE_MASK;
- Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
- iowrite32(Command_Reg, port_base + SATA_COMMAND);
- udelay(20); /* FIXME: flush */
-
- /* write value to register */
- iowrite32((ap->ctl | ATA_SRST) << 24, port_base + ORB4);
-
- /* command the core to send a control FIS */
- Command_Reg &= ~SATA_OPCODE_MASK;
- Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
- iowrite32(Command_Reg, port_base + SATA_COMMAND);
- udelay(20); /* FIXME: flush */
-
- /* write value to register */
- iowrite32((ap->ctl) << 24, port_base + ORB4);
-
- /* command the core to send a control FIS */
- Command_Reg &= ~SATA_OPCODE_MASK;
- Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
- iowrite32(Command_Reg, port_base + SATA_COMMAND);
-
- msleep(150);
-
- rc = ata_sff_wait_ready(link, deadline);
-
- /* if link is occupied, -ENODEV too is an error */
- if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
- ata_link_err(link, "SRST failed (errno=%d)\n", rc);
- return rc;
- }
-
- /* determine by signature whether we have ATA or ATAPI devices */
- sata_oxnas_tf_read(ap, &tf);
- *class = ata_dev_classify(&tf);
-
- if (*class == ATA_DEV_UNKNOWN)
- *class = ATA_DEV_NONE;
-
-out:
- DPRINTK("EXIT, class=%u\n", *class);
- return 0;
-}
-
-
-int sata_oxnas_init_controller(struct ata_host *host)
-{
- return 0;
-}
-
-/**
- * Ref bug-6320
- *
- * This code is a work around for a DMA hardware bug that will repeat the
- * penultimate 8-bytes on some reads. This code will check that the amount
- * of data transferred is a multiple of 512 bytes, if not the in it will
- * fetch the correct data from a buffer in the SATA core and copy it into
- * memory.
- *
- * @param port SATA port to check and if necessary, correct.
- */
-static int sata_oxnas_bug_6320_detect(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- void __iomem *core_base = pd->core_base;
- int is_read;
- int quads_transferred;
- int remainder;
- int sector_quads_remaining;
- int bug_present = 0;
-
- /* Only want to apply fix to reads */
- is_read = !(ioread32(core_base + DM_DBG1) & (ap->port_no ?
- BIT(CORE_PORT1_DATA_DIR_BIT) :
- BIT(CORE_PORT0_DATA_DIR_BIT)));
-
- /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
- transferred (datacount_port register counts quads transferred) */
- quads_transferred =
- ioread32(core_base + (ap->port_no ?
- DATACOUNT_PORT1 : DATACOUNT_PORT0));
-
- remainder = quads_transferred & 0x7f;
- sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
-
- if (is_read && (sector_quads_remaining == 2)) {
- bug_present = 1;
- } else if (sector_quads_remaining) {
- if (is_read) {
- ata_port_warn(ap, "SATA read fixup cannot deal with "
- "%d quads remaining\n",
- sector_quads_remaining);
- } else {
- ata_port_warn(ap, "SATA write fixup of %d quads "
- "remaining not supported\n",
- sector_quads_remaining);
- }
- }
-
- return bug_present;
-}
-
-/* This port done an interrupt */
-static void sata_oxnas_port_irq(struct ata_port *ap, int force_error)
-{
- struct ata_queued_cmd *qc;
- struct sata_oxnas_port_priv *pd = ap->private_data;
- void __iomem *port_base = pd->port_base;
-
- u32 int_status;
- unsigned long flags = 0;
-
- DPRINTK("ENTER port %d irqstatus %x\n", ap->port_no,
- ioread32(port_base + INT_STATUS));
-
- if (ap->qc_active & (1ULL << ATA_TAG_INTERNAL)) {
- qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
- DPRINTK("completing non-ncq cmd\n");
-
- if (qc)
- ata_qc_complete(qc);
-
- return;
- }
-
- qc = ata_qc_from_tag(ap, ap->link.active_tag);
-
-
- /* record the port's interrupt */
- int_status = ioread32(port_base + INT_STATUS);
-
- /* If there's no command associated with this IRQ, ignore it. We may get
- * spurious interrupts when cleaning-up after a failed command, ignore
- * these too. */
- if (likely(qc)) {
- /* get the status before any error cleanup */
- qc->err_mask = ac_err_mask(sata_oxnas_check_status(ap));
- if (force_error) {
- /* Pretend there has been a link error */
- qc->err_mask |= AC_ERR_ATA_BUS;
- DPRINTK(" ####force error####\n");
- }
- /* tell libata we're done */
- local_irq_save(flags);
- sata_oxnas_irq_clear(ap);
- local_irq_restore(flags);
- ata_qc_complete(qc);
- } else {
- VPRINTK("Ignoring interrupt, can't find the command tag="
- "%d %08x\n", ap->link.active_tag, ap->qc_active);
- }
-
- /* maybe a hotplug event */
- if (unlikely(int_status & INT_LINK_SERROR)) {
- u32 serror;
-
- sata_oxnas_scr_read_port(ap, SCR_ERROR, &serror);
- if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
- ata_ehi_hotplugged(&ap->link.eh_info);
- ata_port_freeze(ap);
- }
- }
-}
-
-/**
- * irq_handler is the interrupt handling routine registered with the system,
- * by libata.
- */
-static irqreturn_t sata_oxnas_interrupt(int irq, void *dev_instance)
-{
- struct ata_host *ah = dev_instance;
- struct sata_oxnas_host_priv *hd = ah->private_data;
- void __iomem *core_base = hd->core_base;
-
- u32 int_status;
- irqreturn_t ret = IRQ_NONE;
- u32 port_no;
- u32 mask;
- int bug_present;
-
- /* loop until there are no more interrupts */
- while ((int_status = (ioread32(core_base + CORE_INT_STATUS)) &
- (COREINT_END | (COREINT_END << 1)))) {
-
- /* clear any interrupt */
- iowrite32(int_status, core_base + CORE_INT_CLEAR);
-
- /* Only need workaround_bug_6320 for single disk systems as dual
- * disk will use uCode which prevents this read underrun problem
- * from occurring.
- * All single disk systems will use port 0 */
- for (port_no = 0; port_no < hd->n_ports; ++port_no) {
- /* check the raw end of command interrupt to see if the
- * port is done */
- mask = (COREINT_END << port_no);
- if (!(int_status & mask))
- continue;
-
- /* this port had an interrupt, clear it */
- iowrite32(mask, core_base + CORE_INT_CLEAR);
- /* check for bug 6320 only if no microcode was loaded */
- bug_present = (hd->current_ucode == UNKNOWN_MODE) &&
- sata_oxnas_bug_6320_detect(ah->ports[port_no]);
-
- sata_oxnas_port_irq(ah->ports[port_no],
- bug_present);
- ret = IRQ_HANDLED;
- }
- }
-
- return ret;
-}
-
-/*
- * scsi mid-layer and libata interface structures
- */
-static struct scsi_host_template sata_oxnas_sht = {
- ATA_NCQ_SHT("sata_oxnas"),
- .can_queue = SATA_OXNAS_QUEUE_DEPTH,
- .sg_tablesize = SATA_OXNAS_MAX_PRD,
- .dma_boundary = ATA_DMA_BOUNDARY,
-};
-
-
-static struct ata_port_operations sata_oxnas_ops = {
- .inherits = &sata_port_ops,
- .qc_prep = sata_oxnas_qc_prep,
- .qc_issue = sata_oxnas_qc_issue,
- .qc_fill_rtf = sata_oxnas_qc_fill_rtf,
- .qc_new = sata_oxnas_qc_new,
- .qc_free = sata_oxnas_qc_free,
-
- .scr_read = sata_oxnas_scr_read,
- .scr_write = sata_oxnas_scr_write,
-
- .freeze = sata_oxnas_freeze,
- .thaw = sata_oxnas_thaw,
- .softreset = sata_oxnas_softreset,
- /* .hardreset = sata_oxnas_hardreset, */
- .postreset = sata_oxnas_postreset,
- .error_handler = sata_oxnas_error_handler,
- .post_internal_cmd = sata_oxnas_post_internal_cmd,
-
- .port_start = sata_oxnas_port_start,
- .port_stop = sata_oxnas_port_stop,
-
- .host_stop = sata_oxnas_host_stop,
- /* .pmp_attach = sata_oxnas_pmp_attach, */
- /* .pmp_detach = sata_oxnas_pmp_detach, */
- .sff_check_status = sata_oxnas_check_status,
- .acquire_hw = sata_oxnas_acquire_hw,
-};
-
-static const struct ata_port_info sata_oxnas_port_info = {
- .flags = SATA_OXNAS_HOST_FLAGS,
- .pio_mask = ATA_PIO4,
- .udma_mask = ATA_UDMA6,
- .port_ops = &sata_oxnas_ops,
-};
-
-static int sata_oxnas_probe(struct platform_device *ofdev)
-{
- int retval = -ENXIO;
- int n_ports = 0;
- void __iomem *port_base = NULL;
- void __iomem *dmactl_base = NULL;
- void __iomem *sgdma_base = NULL;
- void __iomem *core_base = NULL;
- void __iomem *phy_base = NULL;
- struct reset_control *rstc;
-
- struct resource res = {};
- struct sata_oxnas_host_priv *host_priv = NULL;
- int irq = 0;
- struct ata_host *host = NULL;
- struct clk *clk = NULL;
-
- const struct ata_port_info *ppi[] = { &sata_oxnas_port_info, NULL };
-
- of_property_read_u32(ofdev->dev.of_node, "nr-ports", &n_ports);
- if (n_ports < 1 || n_ports > SATA_OXNAS_MAX_PORTS)
- goto error_exit_with_cleanup;
-
- port_base = of_iomap(ofdev->dev.of_node, 0);
- if (!port_base)
- goto error_exit_with_cleanup;
-
- dmactl_base = of_iomap(ofdev->dev.of_node, 1);
- if (!dmactl_base)
- goto error_exit_with_cleanup;
-
- sgdma_base = of_iomap(ofdev->dev.of_node, 2);
- if (!sgdma_base)
- goto error_exit_with_cleanup;
-
- core_base = of_iomap(ofdev->dev.of_node, 3);
- if (!core_base)
- goto error_exit_with_cleanup;
-
- phy_base = of_iomap(ofdev->dev.of_node, 4);
- if (!phy_base)
- goto error_exit_with_cleanup;
-
- host_priv = devm_kzalloc(&ofdev->dev,
- sizeof(struct sata_oxnas_host_priv),
- GFP_KERNEL);
- if (!host_priv)
- goto error_exit_with_cleanup;
-
- host_priv->port_base = port_base;
- host_priv->dmactl_base = dmactl_base;
- host_priv->sgdma_base = sgdma_base;
- host_priv->core_base = core_base;
- host_priv->phy_base = phy_base;
- host_priv->n_ports = n_ports;
- host_priv->current_ucode = UNKNOWN_MODE;
-
- if (!of_address_to_resource(ofdev->dev.of_node, 5, &res)) {
- host_priv->dma_base = res.start;
- host_priv->dma_size = resource_size(&res);
- }
-
- irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
- if (!irq) {
- dev_err(&ofdev->dev, "invalid irq from platform\n");
- goto error_exit_with_cleanup;
- }
- host_priv->irq = irq;
-
- clk = of_clk_get(ofdev->dev.of_node, 0);
- if (IS_ERR(clk)) {
- retval = PTR_ERR(clk);
- clk = NULL;
- goto error_exit_with_cleanup;
- }
- host_priv->clk = clk;
-
- rstc = devm_reset_control_get(&ofdev->dev, "sata");
- if (IS_ERR(rstc)) {
- retval = PTR_ERR(rstc);
- goto error_exit_with_cleanup;
- }
- host_priv->rst_sata = rstc;
-
- rstc = devm_reset_control_get(&ofdev->dev, "link");
- if (IS_ERR(rstc)) {
- retval = PTR_ERR(rstc);
- goto error_exit_with_cleanup;
- }
- host_priv->rst_link = rstc;
-
- rstc = devm_reset_control_get(&ofdev->dev, "phy");
- if (IS_ERR(rstc)) {
- retval = PTR_ERR(rstc);
- goto error_exit_with_cleanup;
- }
- host_priv->rst_phy = rstc;
-
- /* allocate host structure */
- host = ata_host_alloc_pinfo(&ofdev->dev, ppi, n_ports);
-
- if (!host) {
- retval = -ENOMEM;
- goto error_exit_with_cleanup;
- }
- host->private_data = host_priv;
- host->iomap = port_base;
-
- /* initialize core locking and queues */
- init_waitqueue_head(&host_priv->fast_wait_queue);
- init_waitqueue_head(&host_priv->scsi_wait_queue);
- spin_lock_init(&host_priv->phy_lock);
- spin_lock_init(&host_priv->core_lock);
- host_priv->core_locked = 0;
- host_priv->reentrant_port_no = -1;
- host_priv->hw_lock_count = 0;
- host_priv->direct_lock_count = 0;
- host_priv->locker_uid = 0;
- host_priv->current_locker_type = SATA_UNLOCKED;
- host_priv->isr_arg = NULL;
- host_priv->isr_callback = NULL;
-
- /* initialize host controller */
- retval = sata_oxnas_init_controller(host);
- if (retval)
- goto error_exit_with_cleanup;
-
- /*
- * Now, register with libATA core, this will also initiate the
- * device discovery process, invoking our port_start() handler &
- * error_handler() to execute a dummy softreset EH session
- */
- ata_host_activate(host, irq, sata_oxnas_interrupt, SATA_OXNAS_IRQ_FLAG,
- &sata_oxnas_sht);
-
- return 0;
-
-error_exit_with_cleanup:
- if (irq)
- irq_dispose_mapping(host_priv->irq);
- if (clk)
- clk_put(clk);
- if (host)
- ata_host_detach(host);
- if (port_base)
- iounmap(port_base);
- if (sgdma_base)
- iounmap(sgdma_base);
- if (core_base)
- iounmap(core_base);
- if (phy_base)
- iounmap(phy_base);
- return retval;
-}
-
-
-static int sata_oxnas_remove(struct platform_device *ofdev)
-{
- struct ata_host *host = dev_get_drvdata(&ofdev->dev);
- struct sata_oxnas_host_priv *host_priv = host->private_data;
-
- ata_host_detach(host);
-
- irq_dispose_mapping(host_priv->irq);
- iounmap(host_priv->port_base);
- iounmap(host_priv->sgdma_base);
- iounmap(host_priv->core_base);
-
- /* reset Controller, Link and PHY */
- reset_control_assert(host_priv->rst_sata);
- reset_control_assert(host_priv->rst_link);
- reset_control_assert(host_priv->rst_phy);
-
- /* Disable the clock to the SATA block */
- clk_disable_unprepare(host_priv->clk);
- clk_put(host_priv->clk);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int sata_oxnas_suspend(struct platform_device *op, pm_message_t state)
-{
- struct ata_host *host = dev_get_drvdata(&op->dev);
-
- return ata_host_suspend(host, state);
-}
-
-static int sata_oxnas_resume(struct platform_device *op)
-{
- struct ata_host *host = dev_get_drvdata(&op->dev);
- int ret;
-
- ret = sata_oxnas_init_controller(host);
- if (ret) {
- dev_err(&op->dev, "Error initializing hardware\n");
- return ret;
- }
- ata_host_resume(host);
- return 0;
-}
-#endif
-
-
-
-static struct of_device_id oxnas_sata_match[] = {
- {
- .compatible = "plxtech,nas782x-sata",
- },
- {},
-};
-
-MODULE_DEVICE_TABLE(of, oxnas_sata_match);
-
-static struct platform_driver oxnas_sata_driver = {
- .driver = {
- .name = "oxnas-sata",
- .owner = THIS_MODULE,
- .of_match_table = oxnas_sata_match,
- },
- .probe = sata_oxnas_probe,
- .remove = sata_oxnas_remove,
-#ifdef CONFIG_PM
- .suspend = sata_oxnas_suspend,
- .resume = sata_oxnas_resume,
-#endif
-};
-
-module_platform_driver(oxnas_sata_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_VERSION("1.0");
-MODULE_AUTHOR("Oxford Semiconductor Ltd.");
-MODULE_DESCRIPTION("low-level driver for Oxford 934 SATA core");
+++ /dev/null
-/*
- * PCIe driver for PLX NAS782X SoCs
- *
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/clk.h>
-#include <linux/module.h>
-#include <linux/mbus.h>
-#include <linux/mfd/syscon.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/of_gpio.h>
-#include <linux/of_irq.h>
-#include <linux/of_pci.h>
-#include <linux/of_platform.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/phy.h>
-#include <linux/phy/phy.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../pci.h"
-
-#define SYS_CTRL_HCSL_CTRL_REGOFFSET 0x114
-
-static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
-{
- u32 val = readl_relaxed(p);
-
- val &= ~mask;
- writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
-{
- u32 val = readl_relaxed(p);
-
- val |= mask;
- writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_value_mask(void __iomem *p,
- unsigned mask, unsigned new_value)
-{
- /* TODO sanity check mask & new_value = new_value */
- u32 val = readl_relaxed(p);
-
- val &= ~mask;
- val |= new_value;
- writel_relaxed(val, p);
-}
-
-#define VERSION_ID_MAGIC 0x082510b5
-#define LINK_UP_TIMEOUT_SECONDS 1
-#define NUM_CONTROLLERS 1
-
-enum {
- PCIE_DEVICE_TYPE_MASK = 0x0F,
- PCIE_DEVICE_TYPE_ENDPOINT = 0,
- PCIE_DEVICE_TYPE_LEGACY_ENDPOINT = 1,
- PCIE_DEVICE_TYPE_ROOT = 4,
-
- PCIE_LTSSM = BIT(4),
- PCIE_READY_ENTR_L23 = BIT(9),
- PCIE_LINK_UP = BIT(11),
- PCIE_OBTRANS = BIT(12),
-};
-
-/* core config registers */
-enum {
- PCI_CONFIG_VERSION_DEVICEID = 0,
- PCI_CONFIG_COMMAND_STATUS = 4,
-};
-
-/* inbound config registers */
-enum {
- IB_ADDR_XLATE_ENABLE = 0xFC,
-
- /* bits */
- ENABLE_IN_ADDR_TRANS = BIT(0),
-};
-
-/* outbound config registers, offset relative to PCIE_POM0_MEM_ADDR */
-enum {
- PCIE_POM0_MEM_ADDR = 0,
- PCIE_POM1_MEM_ADDR = 4,
- PCIE_IN0_MEM_ADDR = 8,
- PCIE_IN1_MEM_ADDR = 12,
- PCIE_IN_IO_ADDR = 16,
- PCIE_IN_CFG0_ADDR = 20,
- PCIE_IN_CFG1_ADDR = 24,
- PCIE_IN_MSG_ADDR = 28,
- PCIE_IN0_MEM_LIMIT = 32,
- PCIE_IN1_MEM_LIMIT = 36,
- PCIE_IN_IO_LIMIT = 40,
- PCIE_IN_CFG0_LIMIT = 44,
- PCIE_IN_CFG1_LIMIT = 48,
- PCIE_IN_MSG_LIMIT = 52,
- PCIE_AHB_SLAVE_CTRL = 56,
-
- PCIE_SLAVE_BE_SHIFT = 22,
-};
-
-#define PCIE_SLAVE_BE(val) ((val) << PCIE_SLAVE_BE_SHIFT)
-#define PCIE_SLAVE_BE_MASK PCIE_SLAVE_BE(0xF)
-
-struct oxnas_pcie_shared {
- /* seems all access are serialized, no lock required */
- int refcount;
-};
-
-/* Structure representing one PCIe interfaces */
-struct oxnas_pcie {
- void __iomem *cfgbase;
- void __iomem *base;
- void __iomem *inbound;
- struct regmap *sys_ctrl;
- unsigned int outbound_offset;
- unsigned int pcie_ctrl_offset;
- struct phy *phy;
- int haslink;
- struct platform_device *pdev;
- struct resource io;
- struct resource cfg;
- struct resource pre_mem; /* prefetchable */
- struct resource non_mem; /* non-prefetchable */
- struct resource busn; /* max available bus numbers */
- int card_reset; /* gpio pin, optional */
- unsigned hcsl_en; /* hcsl pci enable bit */
- struct clk *clk;
- struct clk *busclk; /* for pcie bus, actually the PLLB */
- void *private_data[1];
- spinlock_t lock;
-};
-
-static struct oxnas_pcie_shared pcie_shared = {
- .refcount = 0,
-};
-
-static inline struct oxnas_pcie *sys_to_pcie(struct pci_sys_data *sys)
-{
- return sys->private_data;
-}
-
-
-static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes)
-{
- regmap_update_bits(pcie->sys_ctrl, pcie->outbound_offset + PCIE_AHB_SLAVE_CTRL,
- PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes));
- wmb();
-}
-
-static int oxnas_pcie_link_up(struct oxnas_pcie *pcie)
-{
- unsigned long end;
- unsigned int val;
-
- /* Poll for PCIE link up */
- end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ);
- while (!time_after(jiffies, end)) {
- regmap_read(pcie->sys_ctrl, pcie->pcie_ctrl_offset, &val);
- if (val & PCIE_LINK_UP)
- return 1;
- }
- return 0;
-}
-
-static void oxnas_pcie_setup_hw(struct oxnas_pcie *pcie)
-{
- /* We won't have any inbound address translation. This allows PCI
- * devices to access anywhere in the AHB address map. Might be regarded
- * as a bit dangerous, but let's get things working before we worry
- * about that
- */
- oxnas_register_clear_mask(pcie->inbound + IB_ADDR_XLATE_ENABLE,
- ENABLE_IN_ADDR_TRANS);
- wmb();
-
- /*
- * Program outbound translation windows
- *
- * Outbound window is what is referred to as "PCI client" region in HRM
- *
- * Could use the larger alternative address space to get >>64M regions
- * for graphics cards etc., but will not bother at this point.
- *
- * IP bug means that AMBA window size must be a power of 2
- *
- * Set mem0 window for first 16MB of outbound window non-prefetchable
- * Set mem1 window for second 16MB of outbound window prefetchable
- * Set io window for next 16MB of outbound window
- * Set cfg0 for final 1MB of outbound window
- *
- * Ignore mem1, cfg1 and msg windows for now as no obvious use cases for
- * 820 that would need them
- *
- * Probably ideally want no offset between mem0 window start as seen by
- * ARM and as seen on PCI bus and get Linux to assign memory regions to
- * PCI devices using the same "PCI client" region start address as seen
- * by ARM
- */
-
- /* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_ADDR, pcie->non_mem.start);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_LIMIT, pcie->non_mem.end);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM0_MEM_ADDR, pcie->non_mem.start);
-
- /* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_ADDR, pcie->pre_mem.start);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_LIMIT, pcie->pre_mem.end);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM1_MEM_ADDR, pcie->pre_mem.start);
-
- /* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_ADDR, pcie->io.start);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_LIMIT, pcie->io.end);
-
-
- /* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_ADDR, pcie->cfg.start);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_LIMIT, pcie->cfg.end);
- wmb();
-
- /* Enable outbound address translation */
- regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset, PCIE_OBTRANS, PCIE_OBTRANS);
- wmb();
-
- /*
- * Program PCIe command register for core to:
- * enable memory space
- * enable bus master
- * enable io
- */
- writel_relaxed(7, pcie->base + PCI_CONFIG_COMMAND_STATUS);
- /* which is which */
- wmb();
-}
-
-static unsigned oxnas_pcie_cfg_to_offset(
- struct pci_sys_data *sys,
- unsigned char bus_number,
- unsigned int devfn,
- int where)
-{
- unsigned int function = PCI_FUNC(devfn);
- unsigned int slot = PCI_SLOT(devfn);
- unsigned char bus_number_offset;
-
- bus_number_offset = bus_number - sys->busnr;
-
- /*
- * We'll assume for now that the offset, function, slot, bus encoding
- * should map onto linear, contiguous addresses in PCIe config space,
- * albeit that the majority will be unused as only slot 0 is valid for
- * any PCIe bus and most devices have only function 0
- *
- * Could be that PCIe in fact works by not encoding the slot number into
- * the config space address as it's known that only slot 0 is valid.
- * We'll have to experiment if/when we get a PCIe switch connected to
- * the PCIe host
- */
- return (bus_number_offset << 20) | (slot << 15) | (function << 12) |
- (where & ~3);
-}
-
-/* PCI configuration space write function */
-static int oxnas_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
- int where, int size, u32 val)
-{
- unsigned long flags;
- struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
- unsigned offset;
- u32 value;
- u32 lanes;
-
- /* Only a single device per bus for PCIe point-to-point links */
- if (PCI_SLOT(devfn) > 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- if (!pcie->haslink)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
- where);
-
- value = val << (8 * (where & 3));
- lanes = (0xf >> (4-size)) << (where & 3);
- /* it race with mem and io write, but the possibility is low, normally
- * all config writes happens at driver initialize stage, wont interleave
- * with others.
- * and many pcie cards use dword (4bytes) access mem/io access only,
- * so not bother to copy that ugly work-around now. */
- spin_lock_irqsave(&pcie->lock, flags);
- set_out_lanes(pcie, lanes);
- writel_relaxed(value, pcie->cfgbase + offset);
- set_out_lanes(pcie, 0xf);
- spin_unlock_irqrestore(&pcie->lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-/* PCI configuration space read function */
-static int oxnas_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
- int size, u32 *val)
-{
- struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
- unsigned offset;
- u32 value;
- u32 left_bytes, right_bytes;
-
- /* Only a single device per bus for PCIe point-to-point links */
- if (PCI_SLOT(devfn) > 0) {
- *val = 0xffffffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- if (!pcie->haslink) {
- *val = 0xffffffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
- where);
- value = readl_relaxed(pcie->cfgbase + offset);
- left_bytes = where & 3;
- right_bytes = 4 - left_bytes - size;
- value <<= right_bytes * 8;
- value >>= (left_bytes + right_bytes) * 8;
- *val = value;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops oxnas_pcie_ops = {
- .read = oxnas_pcie_rd_conf,
- .write = oxnas_pcie_wr_conf,
-};
-
-static int oxnas_pcie_setup(int nr, struct pci_sys_data *sys)
-{
- struct oxnas_pcie *pcie = sys_to_pcie(sys);
-
- pci_add_resource_offset(&sys->resources, &pcie->non_mem, sys->mem_offset);
- pci_add_resource_offset(&sys->resources, &pcie->pre_mem, sys->mem_offset);
- pci_add_resource_offset(&sys->resources, &pcie->io, sys->io_offset);
- pci_add_resource(&sys->resources, &pcie->busn);
- if (sys->busnr == 0) { /* default one */
- sys->busnr = pcie->busn.start;
- }
- /* do not use devm_ioremap_resource, it does not like cfg resource */
- pcie->cfgbase = devm_ioremap(&pcie->pdev->dev, pcie->cfg.start,
- resource_size(&pcie->cfg));
- if (!pcie->cfgbase)
- return -ENOMEM;
-
- oxnas_pcie_setup_hw(pcie);
-
- return 1;
-}
-
-static void oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie)
-{
- struct hw_pci hw;
- int i;
-
- memset(&hw, 0, sizeof(hw));
- for (i = 0; i < NUM_CONTROLLERS; i++)
- pcie->private_data[i] = pcie;
-
- hw.nr_controllers = NUM_CONTROLLERS;
-/* I think use stack pointer is a bad idea though it is valid in this case */
- hw.private_data = pcie->private_data;
- hw.setup = oxnas_pcie_setup;
- hw.map_irq = of_irq_parse_and_map_pci;
- hw.ops = &oxnas_pcie_ops;
-
- /* pass dev to maintain of tree, interrupt mapping rely on this */
- pci_common_init_dev(dev, &hw);
-}
-
-static int oxnas_pcie_shared_init(struct platform_device *pdev, struct oxnas_pcie *pcie)
-{
- if (++pcie_shared.refcount == 1) {
- phy_init(pcie->phy);
- phy_power_on(pcie->phy);
- return 0;
- } else {
- return 0;
- }
-}
-
-#if 0
-/* maybe we will call it when enter low power state */
-static void oxnas_pcie_shared_deinit(struct platform_device *pdev)
-{
- if (--pcie_shared.refcount == 0) {
- /* no cleanup needed */;
- }
-}
-#endif
-
-static int
-oxnas_pcie_map_registers(struct platform_device *pdev,
- struct device_node *np,
- struct oxnas_pcie *pcie)
-{
- struct resource regs;
- int ret = 0;
- u32 outbound_ctrl_offset;
- u32 pcie_ctrl_offset;
-
- ret = of_address_to_resource(np, 0, ®s);
- if (ret) {
- dev_err(&pdev->dev, "failed to parse base register space\n");
- return -EINVAL;
- }
-
- pcie->base = devm_ioremap_resource(&pdev->dev, ®s);
- if (!pcie->base) {
- dev_err(&pdev->dev, "failed to map base register space\n");
- return -ENOMEM;
- }
-
- ret = of_address_to_resource(np, 1, ®s);
- if (ret) {
- dev_err(&pdev->dev, "failed to parse inbound register space\n");
- return -EINVAL;
- }
-
- pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s);
- if (!pcie->inbound) {
- dev_err(&pdev->dev, "failed to map inbound register space\n");
- return -ENOMEM;
- }
-
- pcie->phy = devm_of_phy_get(&pdev->dev, np, NULL);
- if (IS_ERR(pcie->phy)) {
- if (PTR_ERR(pcie->phy) == -EPROBE_DEFER) {
- dev_err(&pdev->dev, "failed to probe phy\n");
- return PTR_ERR(pcie->phy);
- }
- dev_warn(&pdev->dev, "phy not attached\n");
- pcie->phy = NULL;
- }
-
- if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
- &outbound_ctrl_offset)) {
- dev_err(&pdev->dev, "failed to parse outbound register offset\n");
- return -EINVAL;
- }
- pcie->outbound_offset = outbound_ctrl_offset;
-
- if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
- &pcie_ctrl_offset)) {
- dev_err(&pdev->dev, "failed to parse pcie-ctrl register offset\n");
- return -EINVAL;
- }
- pcie->pcie_ctrl_offset = pcie_ctrl_offset;
-
- return 0;
-}
-
-static int oxnas_pcie_init_res(struct platform_device *pdev,
- struct oxnas_pcie *pcie,
- struct device_node *np)
-{
- struct of_pci_range range;
- struct of_pci_range_parser parser;
- int ret;
-
- if (of_pci_range_parser_init(&parser, np))
- return -EINVAL;
-
- /* Get the I/O and memory ranges from DT */
- for_each_of_pci_range(&parser, &range) {
-
- unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
- if (restype == IORESOURCE_IO) {
- of_pci_range_to_resource(&range, np, &pcie->io);
- pcie->io.name = "I/O";
- }
- if (restype == IORESOURCE_MEM) {
- if (range.flags & IORESOURCE_PREFETCH) {
- of_pci_range_to_resource(&range, np, &pcie->pre_mem);
- pcie->pre_mem.name = "PRE MEM";
- } else {
- of_pci_range_to_resource(&range, np, &pcie->non_mem);
- pcie->non_mem.name = "NON MEM";
- }
-
- }
- if (restype == 0)
- of_pci_range_to_resource(&range, np, &pcie->cfg);
- }
-
- /* Get the bus range */
- ret = of_pci_parse_bus_range(np, &pcie->busn);
-
- if (ret) {
- dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
- ret);
- return ret;
- }
-
- pcie->card_reset = of_get_gpio(np, 0);
- if (pcie->card_reset < 0)
- dev_info(&pdev->dev, "card reset gpio pin not exists\n");
-
- if (of_property_read_u32(np, "plxtech,pcie-hcsl-bit", &pcie->hcsl_en))
- return -EINVAL;
-
- pcie->clk = of_clk_get_by_name(np, "pcie");
- if (IS_ERR(pcie->clk)) {
- return PTR_ERR(pcie->clk);
- }
-
- pcie->busclk = of_clk_get_by_name(np, "busclk");
- if (IS_ERR(pcie->busclk)) {
- clk_put(pcie->clk);
- return PTR_ERR(pcie->busclk);
- }
-
- return 0;
-}
-
-static void oxnas_pcie_init_hw(struct platform_device *pdev,
- struct oxnas_pcie *pcie)
-{
- u32 version_id;
- int ret;
-
- clk_prepare_enable(pcie->busclk);
-
- /* reset PCIe cards use hard-wired gpio pin */
- if (pcie->card_reset >= 0 &&
- !gpio_direction_output(pcie->card_reset, 0)) {
- wmb();
- mdelay(10);
- /* must tri-state the pin to pull it up */
- gpio_direction_input(pcie->card_reset);
- wmb();
- mdelay(100);
- }
-
- /* ToDo: use phy power-on port... */
- regmap_update_bits(pcie->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET,
- BIT(pcie->hcsl_en), BIT(pcie->hcsl_en));
-
- /* core */
- ret = device_reset(&pdev->dev);
- if (ret) {
- dev_err(&pdev->dev, "core reset failed %d\n", ret);
- return;
- }
-
- /* Start PCIe core clocks */
- clk_prepare_enable(pcie->clk);
-
- version_id = readl_relaxed(pcie->base + PCI_CONFIG_VERSION_DEVICEID);
- dev_info(&pdev->dev, "PCIe version/deviceID 0x%x\n", version_id);
-
- if (version_id != VERSION_ID_MAGIC) {
- dev_info(&pdev->dev, "PCIe controller not found\n");
- pcie->haslink = 0;
- return;
- }
-
- /* allow entry to L23 state */
- regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
- PCIE_READY_ENTR_L23, PCIE_READY_ENTR_L23);
-
- /* Set PCIe core into RootCore mode */
- regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
- PCIE_DEVICE_TYPE_MASK, PCIE_DEVICE_TYPE_ROOT);
- wmb();
-
- /* Bring up the PCI core */
- regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
- PCIE_LTSSM, PCIE_LTSSM);
- wmb();
-}
-
-static int oxnas_pcie_probe(struct platform_device *pdev)
-{
- struct oxnas_pcie *pcie;
- struct device_node *np = pdev->dev.of_node;
- int ret;
-
- pcie = devm_kzalloc(&pdev->dev, sizeof(struct oxnas_pcie),
- GFP_KERNEL);
- if (!pcie)
- return -ENOMEM;
-
- pcie->pdev = pdev;
- pcie->haslink = 1;
- spin_lock_init(&pcie->lock);
-
- pcie->sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
- if (IS_ERR(pcie->sys_ctrl))
- return PTR_ERR(pcie->sys_ctrl);
-
- ret = oxnas_pcie_init_res(pdev, pcie, np);
- if (ret)
- return ret;
- if (pcie->card_reset >= 0) {
- ret = gpio_request_one(pcie->card_reset, GPIOF_DIR_IN,
- dev_name(&pdev->dev));
- if (ret) {
- dev_err(&pdev->dev, "cannot request gpio pin %d\n",
- pcie->card_reset);
- return ret;
- }
- }
-
- ret = oxnas_pcie_map_registers(pdev, np, pcie);
- if (ret) {
- dev_err(&pdev->dev, "cannot map registers\n");
- goto err_free_gpio;
- }
-
- ret = oxnas_pcie_shared_init(pdev, pcie);
- if (ret)
- goto err_free_gpio;
-
- /* if hw not found, haslink cleared */
- oxnas_pcie_init_hw(pdev, pcie);
-
- if (pcie->haslink && oxnas_pcie_link_up(pcie)) {
- pcie->haslink = 1;
- dev_info(&pdev->dev, "link up\n");
- } else {
- pcie->haslink = 0;
- dev_info(&pdev->dev, "link down\n");
- }
- /* should we register our controller even when pcie->haslink is 0 ? */
- /* register the controller with framework */
- oxnas_pcie_enable(&pdev->dev, pcie);
-
- return 0;
-
-err_free_gpio:
- if (pcie->card_reset)
- gpio_free(pcie->card_reset);
-
- return ret;
-}
-
-static const struct of_device_id oxnas_pcie_of_match_table[] = {
- { .compatible = "plxtech,nas782x-pcie", },
- {},
-};
-
-static struct platform_driver oxnas_pcie_driver = {
- .driver = {
- .name = "oxnas-pcie",
- .suppress_bind_attrs = true,
- .of_match_table = oxnas_pcie_of_match_table,
- },
- .probe = oxnas_pcie_probe,
-};
-
-builtin_platform_driver(oxnas_pcie_driver);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- *
- */
-
-#include <dt-bindings/phy/phy.h>
-#include <linux/io.h>
-#include <linux/iopoll.h>
-#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/mfd/syscon.h>
-#include <linux/phy/phy.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-
-#define ADDR_VAL(val) ((val) & 0xFFFF)
-#define DATA_VAL(val) ((val) & 0xFFFF)
-
-#define SYS_CTRL_HCSL_CTRL_REGOFFSET 0x114
-
-enum {
- HCSL_BIAS_ON = BIT(0),
- HCSL_PCIE_EN = BIT(1),
- HCSL_PCIEA_EN = BIT(2),
- HCSL_PCIEB_EN = BIT(3),
-};
-
-enum {
- /* pcie phy reg offset */
- PHY_ADDR = 0,
- PHY_DATA = 4,
- /* phy data reg bits */
- READ_EN = BIT(16),
- WRITE_EN = BIT(17),
- CAP_DATA = BIT(18),
-};
-
-struct oxnas_pcie_phy {
- struct device *dev;
- void __iomem *membase;
- const struct phy_ops *ops;
- struct regmap *sys_ctrl;
- struct reset_control *rstc;
-};
-
-static int oxnas_pcie_phy_init(struct phy *phy)
-{
- struct oxnas_pcie_phy *pciephy = phy_get_drvdata(phy);
- int ret;
-
- /* generate clocks from HCSL buffers, shared parts */
- regmap_write(pciephy->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET, HCSL_BIAS_ON|HCSL_PCIE_EN);
-
- /* Ensure PCIe PHY is properly reset */
- ret = reset_control_reset(pciephy->rstc);
-
- if (ret) {
- dev_err(pciephy->dev, "phy reset failed %d\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-static int oxnas_pcie_phy_power_on(struct phy *phy)
-{
- struct oxnas_pcie_phy *pciephy = phy_get_drvdata(phy);
-
- /* Enable PCIe Pre-Emphasis: What these value means? */
- writel(ADDR_VAL(0x0014), pciephy->membase + PHY_ADDR);
- writel(DATA_VAL(0xce10) | CAP_DATA, pciephy->membase + PHY_DATA);
- writel(DATA_VAL(0xce10) | WRITE_EN, pciephy->membase + PHY_DATA);
-
- writel(ADDR_VAL(0x2004), pciephy->membase + PHY_ADDR);
- writel(DATA_VAL(0x82c7) | CAP_DATA, pciephy->membase + PHY_DATA);
- writel(DATA_VAL(0x82c7) | WRITE_EN, pciephy->membase + PHY_DATA);
-
- return 0;
-}
-
-static const struct phy_ops ops = {
- .init = oxnas_pcie_phy_init,
- .power_on = oxnas_pcie_phy_power_on,
- .owner = THIS_MODULE,
-};
-
-static int oxnas_pcie_phy_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct device_node *np = pdev->dev.of_node;
- struct phy *generic_phy;
- struct phy_provider *phy_provider;
- struct oxnas_pcie_phy *pciephy;
- struct regmap *sys_ctrl;
- struct reset_control *rstc;
- void __iomem *membase;
-
- membase = of_iomap(np, 0);
- if (IS_ERR(membase))
- return PTR_ERR(membase);
-
- sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
- if (IS_ERR(sys_ctrl))
- return PTR_ERR(sys_ctrl);
-
- rstc = devm_reset_control_get_shared(dev, "phy");
- if (IS_ERR(rstc))
- return PTR_ERR(rstc);
-
- pciephy = devm_kzalloc(dev, sizeof(*pciephy), GFP_KERNEL);
- if (!pciephy)
- return -ENOMEM;
-
- pciephy->sys_ctrl = sys_ctrl;
- pciephy->rstc = rstc;
- pciephy->membase = membase;
- pciephy->dev = dev;
- pciephy->ops = &ops;
-
- generic_phy = devm_phy_create(dev, dev->of_node, pciephy->ops);
- if (IS_ERR(generic_phy)) {
- dev_err(dev, "failed to create PHY\n");
- return PTR_ERR(generic_phy);
- }
-
- phy_set_drvdata(generic_phy, pciephy);
- phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-
- return PTR_ERR_OR_ZERO(phy_provider);
-}
-
-static const struct of_device_id oxnas_pcie_phy_id_table[] = {
- { .compatible = "oxsemi,ox820-pcie-phy" },
- { },
-};
-
-static struct platform_driver oxnas_pcie_phy_driver = {
- .probe = oxnas_pcie_phy_probe,
- .driver = {
- .name = "ox820-pcie-phy",
- .of_match_table = oxnas_pcie_phy_id_table,
- },
-};
-
-builtin_platform_driver(oxnas_pcie_phy_driver);
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * oxnas SoC reset driver
- * based on:
- * Microsemi MIPS SoC reset driver
- *
- * License: GPL
- * Copyright (c) 2017 Microsemi Corporation
- */
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/notifier.h>
-#include <linux/mfd/syscon.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/reboot.h>
-#include <linux/regmap.h>
-
-/* bit numbers of reset control register */
-#define OX820_SYS_CTRL_RST_SCU 0
-#define OX820_SYS_CTRL_RST_COPRO 1
-#define OX820_SYS_CTRL_RST_ARM0 2
-#define OX820_SYS_CTRL_RST_ARM1 3
-#define OX820_SYS_CTRL_RST_USBHS 4
-#define OX820_SYS_CTRL_RST_USBHSPHYA 5
-#define OX820_SYS_CTRL_RST_MACA 6
-#define OX820_SYS_CTRL_RST_MAC OX820_SYS_CTRL_RST_MACA
-#define OX820_SYS_CTRL_RST_PCIEA 7
-#define OX820_SYS_CTRL_RST_SGDMA 8
-#define OX820_SYS_CTRL_RST_CIPHER 9
-#define OX820_SYS_CTRL_RST_DDR 10
-#define OX820_SYS_CTRL_RST_SATA 11
-#define OX820_SYS_CTRL_RST_SATA_LINK 12
-#define OX820_SYS_CTRL_RST_SATA_PHY 13
-#define OX820_SYS_CTRL_RST_PCIEPHY 14
-#define OX820_SYS_CTRL_RST_STATIC 15
-#define OX820_SYS_CTRL_RST_GPIO 16
-#define OX820_SYS_CTRL_RST_UART1 17
-#define OX820_SYS_CTRL_RST_UART2 18
-#define OX820_SYS_CTRL_RST_MISC 19
-#define OX820_SYS_CTRL_RST_I2S 20
-#define OX820_SYS_CTRL_RST_SD 21
-#define OX820_SYS_CTRL_RST_MACB 22
-#define OX820_SYS_CTRL_RST_PCIEB 23
-#define OX820_SYS_CTRL_RST_VIDEO 24
-#define OX820_SYS_CTRL_RST_DDR_PHY 25
-#define OX820_SYS_CTRL_RST_USBHSPHYB 26
-#define OX820_SYS_CTRL_RST_USBDEV 27
-#define OX820_SYS_CTRL_RST_ARMDBG 29
-#define OX820_SYS_CTRL_RST_PLLA 30
-#define OX820_SYS_CTRL_RST_PLLB 31
-
-/* bit numbers of clock control register */
-#define OX820_SYS_CTRL_CLK_COPRO 0
-#define OX820_SYS_CTRL_CLK_DMA 1
-#define OX820_SYS_CTRL_CLK_CIPHER 2
-#define OX820_SYS_CTRL_CLK_SD 3
-#define OX820_SYS_CTRL_CLK_SATA 4
-#define OX820_SYS_CTRL_CLK_I2S 5
-#define OX820_SYS_CTRL_CLK_USBHS 6
-#define OX820_SYS_CTRL_CLK_MACA 7
-#define OX820_SYS_CTRL_CLK_MAC OX820_SYS_CTRL_CLK_MACA
-#define OX820_SYS_CTRL_CLK_PCIEA 8
-#define OX820_SYS_CTRL_CLK_STATIC 9
-#define OX820_SYS_CTRL_CLK_MACB 10
-#define OX820_SYS_CTRL_CLK_PCIEB 11
-#define OX820_SYS_CTRL_CLK_REF600 12
-#define OX820_SYS_CTRL_CLK_USBDEV 13
-#define OX820_SYS_CTRL_CLK_DDR 14
-#define OX820_SYS_CTRL_CLK_DDRPHY 15
-#define OX820_SYS_CTRL_CLK_DDRCK 16
-
-/* Regmap offsets */
-#define OX820_CLK_SET_REGOFFSET 0x2c
-#define OX820_CLK_CLR_REGOFFSET 0x30
-#define OX820_RST_SET_REGOFFSET 0x34
-#define OX820_RST_CLR_REGOFFSET 0x38
-#define OX820_SECONDARY_SEL_REGOFFSET 0x14
-#define OX820_TERTIARY_SEL_REGOFFSET 0x8c
-#define OX820_QUATERNARY_SEL_REGOFFSET 0x94
-#define OX820_DEBUG_SEL_REGOFFSET 0x9c
-#define OX820_ALTERNATIVE_SEL_REGOFFSET 0xa4
-#define OX820_PULLUP_SEL_REGOFFSET 0xac
-#define OX820_SEC_SECONDARY_SEL_REGOFFSET 0x100014
-#define OX820_SEC_TERTIARY_SEL_REGOFFSET 0x10008c
-#define OX820_SEC_QUATERNARY_SEL_REGOFFSET 0x100094
-#define OX820_SEC_DEBUG_SEL_REGOFFSET 0x10009c
-#define OX820_SEC_ALTERNATIVE_SEL_REGOFFSET 0x1000a4
-#define OX820_SEC_PULLUP_SEL_REGOFFSET 0x1000ac
-
-
-struct oxnas_restart_context {
- struct regmap *sys_ctrl;
- struct notifier_block restart_handler;
-};
-
-static int ox820_restart_handle(struct notifier_block *this,
- unsigned long mode, void *cmd)
-{
- struct oxnas_restart_context *ctx = container_of(this, struct
- oxnas_restart_context,
- restart_handler);
- u32 value;
-
- /* Assert reset to cores as per power on defaults
- * Don't touch the DDR interface as things will come to an impromptu stop
- * NB Possibly should be asserting reset for PLLB, but there are timing
- * concerns here according to the docs */
- value = BIT(OX820_SYS_CTRL_RST_COPRO) |
- BIT(OX820_SYS_CTRL_RST_USBHS) |
- BIT(OX820_SYS_CTRL_RST_USBHSPHYA) |
- BIT(OX820_SYS_CTRL_RST_MACA) |
- BIT(OX820_SYS_CTRL_RST_PCIEA) |
- BIT(OX820_SYS_CTRL_RST_SGDMA) |
- BIT(OX820_SYS_CTRL_RST_CIPHER) |
- BIT(OX820_SYS_CTRL_RST_SATA) |
- BIT(OX820_SYS_CTRL_RST_SATA_LINK) |
- BIT(OX820_SYS_CTRL_RST_SATA_PHY) |
- BIT(OX820_SYS_CTRL_RST_PCIEPHY) |
- BIT(OX820_SYS_CTRL_RST_STATIC) |
- BIT(OX820_SYS_CTRL_RST_UART1) |
- BIT(OX820_SYS_CTRL_RST_UART2) |
- BIT(OX820_SYS_CTRL_RST_MISC) |
- BIT(OX820_SYS_CTRL_RST_I2S) |
- BIT(OX820_SYS_CTRL_RST_SD) |
- BIT(OX820_SYS_CTRL_RST_MACB) |
- BIT(OX820_SYS_CTRL_RST_PCIEB) |
- BIT(OX820_SYS_CTRL_RST_VIDEO) |
- BIT(OX820_SYS_CTRL_RST_USBHSPHYB) |
- BIT(OX820_SYS_CTRL_RST_USBDEV);
-
- regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
-
- /* Release reset to cores as per power on defaults */
- regmap_write(ctx->sys_ctrl, OX820_RST_CLR_REGOFFSET, BIT(OX820_SYS_CTRL_RST_GPIO));
-
- /* Disable clocks to cores as per power-on defaults - must leave DDR
- * related clocks enabled otherwise we'll stop rather abruptly. */
- value =
- BIT(OX820_SYS_CTRL_CLK_COPRO) |
- BIT(OX820_SYS_CTRL_CLK_DMA) |
- BIT(OX820_SYS_CTRL_CLK_CIPHER) |
- BIT(OX820_SYS_CTRL_CLK_SD) |
- BIT(OX820_SYS_CTRL_CLK_SATA) |
- BIT(OX820_SYS_CTRL_CLK_I2S) |
- BIT(OX820_SYS_CTRL_CLK_USBHS) |
- BIT(OX820_SYS_CTRL_CLK_MAC) |
- BIT(OX820_SYS_CTRL_CLK_PCIEA) |
- BIT(OX820_SYS_CTRL_CLK_STATIC) |
- BIT(OX820_SYS_CTRL_CLK_MACB) |
- BIT(OX820_SYS_CTRL_CLK_PCIEB) |
- BIT(OX820_SYS_CTRL_CLK_REF600) |
- BIT(OX820_SYS_CTRL_CLK_USBDEV);
-
- regmap_write(ctx->sys_ctrl, OX820_CLK_CLR_REGOFFSET, value);
-
- /* Enable clocks to cores as per power-on defaults */
-
- /* Set sys-control pin mux'ing as per power-on defaults */
- regmap_write(ctx->sys_ctrl, OX820_SECONDARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_TERTIARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_QUATERNARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_DEBUG_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_ALTERNATIVE_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_PULLUP_SEL_REGOFFSET, 0);
-
- regmap_write(ctx->sys_ctrl, OX820_SEC_SECONDARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_TERTIARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_QUATERNARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_DEBUG_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_ALTERNATIVE_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_PULLUP_SEL_REGOFFSET, 0);
-
- /* No need to save any state, as the ROM loader can determine whether
- * reset is due to power cycling or programatic action, just hit the
- * (self-clearing) CPU reset bit of the block reset register */
- value =
- BIT(OX820_SYS_CTRL_RST_SCU) |
- BIT(OX820_SYS_CTRL_RST_ARM0) |
- BIT(OX820_SYS_CTRL_RST_ARM1);
-
- regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
-
- pr_emerg("Unable to restart system\n");
- return NOTIFY_DONE;
-}
-
-static int ox820_restart_probe(struct platform_device *pdev)
-{
- struct oxnas_restart_context *ctx;
- struct regmap *sys_ctrl;
- struct device *dev = &pdev->dev;
- int err = 0;
-
- sys_ctrl = syscon_node_to_regmap(pdev->dev.of_node);
- if (IS_ERR(sys_ctrl))
- return PTR_ERR(sys_ctrl);
-
- ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
- if (!ctx)
- return -ENOMEM;
-
- ctx->sys_ctrl = sys_ctrl;
- ctx->restart_handler.notifier_call = ox820_restart_handle;
- ctx->restart_handler.priority = 192;
- err = register_restart_handler(&ctx->restart_handler);
- if (err)
- dev_err(dev, "can't register restart notifier (err=%d)\n", err);
-
- return err;
-}
-
-static const struct of_device_id ox820_restart_of_match[] = {
- { .compatible = "oxsemi,ox820-sys-ctrl" },
- {}
-};
-
-static struct platform_driver ox820_restart_driver = {
- .probe = ox820_restart_probe,
- .driver = {
- .name = "ox820-chip-reset",
- .of_match_table = ox820_restart_of_match,
- },
-};
-builtin_platform_driver(ox820_restart_driver);
+++ /dev/null
-/*
- * drivers/usb/host/ehci-oxnas.c
- *
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/mfd/syscon.h>
-#include <linux/usb.h>
-#include <linux/usb/hcd.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-
-#define USBHSMPH_CTRL_REGOFFSET 0x40
-#define USBHSMPH_STAT_REGOFFSET 0x44
-#define REF300_DIV_REGOFFSET 0xF8
-#define USBHSPHY_CTRL_REGOFFSET 0x84
-#define USB_CTRL_REGOFFSET 0x90
-#define PLLB_DIV_CTRL_REGOFFSET 0x1000F8
-#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16
-#define USBHSPHY_SUSPENDM_MANUAL_STATE 15
-#define USBHSPHY_ATE_ESET 14
-#define USBHSPHY_TEST_DIN 6
-#define USBHSPHY_TEST_ADD 2
-#define USBHSPHY_TEST_DOUT_SEL 1
-#define USBHSPHY_TEST_CLK 0
-
-#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5
-#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-
-#define USBAMUX_DEVICE BIT(4)
-
-#define USBPHY_REFCLKDIV_SHIFT 2
-#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT)
-
-#define USB_CTRL_USB_CKO_SEL_BIT 0
-
-#define USB_INT_CLK_XTAL 0
-#define USB_INT_CLK_REF300 2
-#define USB_INT_CLK_PLLB 3
-
-#define REF300_DIV_INT_SHIFT 8
-#define REF300_DIV_FRAC_SHIFT 0
-#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
-#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
-
-#define PLLB_BYPASS 1
-#define PLLB_ENSAT 3
-#define PLLB_OUTDIV 4
-#define PLLB_REFDIV 8
-#define PLLB_DIV_INT_SHIFT 8
-#define PLLB_DIV_FRAC_SHIFT 0
-#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
-#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
-
-#include "ehci.h"
-
-struct oxnas_hcd {
- struct clk *clk;
- struct clk *refsrc;
- struct clk *phyref;
- int use_pllb;
- int use_phya;
- struct reset_control *rst_host;
- struct reset_control *rst_phya;
- struct reset_control *rst_phyb;
- struct regmap *syscon;
-};
-
-#define DRIVER_DESC "Oxnas On-Chip EHCI Host Controller"
-
-static struct hc_driver __read_mostly oxnas_hc_driver;
-
-static void start_oxnas_usb_ehci(struct oxnas_hcd *oxnas)
-{
- if (oxnas->use_pllb) {
- /* enable pllb */
- clk_prepare_enable(oxnas->refsrc);
- /* enable ref600 */
- clk_prepare_enable(oxnas->phyref);
- /* 600MHz pllb divider for 12MHz */
- regmap_write_bits(oxnas->syscon, PLLB_DIV_CTRL_REGOFFSET, 0xffff, PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0));
- } else {
- /* ref 300 divider for 12MHz */
- regmap_write_bits(oxnas->syscon, REF300_DIV_REGOFFSET, 0xffff, REF300_DIV_INT(25) | REF300_DIV_FRAC(0));
- }
-
- /* Ensure the USB block is properly reset */
- reset_control_reset(oxnas->rst_host);
- reset_control_reset(oxnas->rst_phya);
- reset_control_reset(oxnas->rst_phyb);
-
- /* Force the high speed clock to be generated all the time, via serial
- programming of the USB HS PHY */
- regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
- (2UL << USBHSPHY_TEST_ADD) |
- (0xe0UL << USBHSPHY_TEST_DIN));
-
- regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
- (1UL << USBHSPHY_TEST_CLK) |
- (2UL << USBHSPHY_TEST_ADD) |
- (0xe0UL << USBHSPHY_TEST_DIN));
-
- regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
- (0xfUL << USBHSPHY_TEST_ADD) |
- (0xaaUL << USBHSPHY_TEST_DIN));
-
- regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
- (1UL << USBHSPHY_TEST_CLK) |
- (0xfUL << USBHSPHY_TEST_ADD) |
- (0xaaUL << USBHSPHY_TEST_DIN));
-
- if (oxnas->use_pllb) /* use pllb clock */
- regmap_write_bits(oxnas->syscon, USB_CTRL_REGOFFSET, 0xffff,
- USB_CLK_INTERNAL | USB_INT_CLK_PLLB);
- else /* use ref300 derived clock */
- regmap_write_bits(oxnas->syscon, USB_CTRL_REGOFFSET, 0xffff,
- USB_CLK_INTERNAL | USB_INT_CLK_REF300);
-
- if (oxnas->use_phya) {
- /* Configure USB PHYA as a host */
- regmap_update_bits(oxnas->syscon, USB_CTRL_REGOFFSET, USBAMUX_DEVICE, 0);
- }
-
- /* Enable the clock to the USB block */
- clk_prepare_enable(oxnas->clk);
-}
-
-static void stop_oxnas_usb_ehci(struct oxnas_hcd *oxnas)
-{
- reset_control_assert(oxnas->rst_host);
- reset_control_assert(oxnas->rst_phya);
- reset_control_assert(oxnas->rst_phyb);
-
- if (oxnas->use_pllb) {
- clk_disable_unprepare(oxnas->phyref);
- clk_disable_unprepare(oxnas->refsrc);
- }
- clk_disable_unprepare(oxnas->clk);
-}
-
-static int ehci_oxnas_reset(struct usb_hcd *hcd)
-{
- #define txttfill_tuning reserved2[0]
-
- struct ehci_hcd *ehci;
- u32 tmp;
- int retval = ehci_setup(hcd);
- if (retval)
- return retval;
-
- ehci = hcd_to_ehci(hcd);
- tmp = ehci_readl(ehci, &ehci->regs->txfill_tuning);
- tmp &= ~0x00ff0000;
- tmp |= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes) */
- tmp |= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/
- ehci_writel(ehci, tmp, &ehci->regs->txfill_tuning);
-
- tmp = ehci_readl(ehci, &ehci->regs->txttfill_tuning);
- tmp |= 0x2; /* set sheduler overhead to 2 * 6.333us */
- ehci_writel(ehci, tmp, &ehci->regs->txttfill_tuning);
-
- return retval;
-}
-
-static int ehci_oxnas_drv_probe(struct platform_device *ofdev)
-{
- struct device_node *np = ofdev->dev.of_node;
- struct usb_hcd *hcd;
- struct ehci_hcd *ehci;
- struct resource res;
- struct oxnas_hcd *oxnas;
- int irq, err;
- struct reset_control *rstc;
-
- if (usb_disabled())
- return -ENODEV;
-
- if (!ofdev->dev.dma_mask)
- ofdev->dev.dma_mask = &ofdev->dev.coherent_dma_mask;
- if (!ofdev->dev.coherent_dma_mask)
- ofdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-
- hcd = usb_create_hcd(&oxnas_hc_driver, &ofdev->dev,
- dev_name(&ofdev->dev));
- if (!hcd)
- return -ENOMEM;
-
- err = of_address_to_resource(np, 0, &res);
- if (err)
- goto err_res;
-
- hcd->rsrc_start = res.start;
- hcd->rsrc_len = resource_size(&res);
-
- hcd->regs = devm_ioremap_resource(&ofdev->dev, &res);
- if (IS_ERR(hcd->regs)) {
- dev_err(&ofdev->dev, "devm_ioremap_resource failed\n");
- err = PTR_ERR(hcd->regs);
- goto err_ioremap;
- }
-
- oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv;
-
- oxnas->use_pllb = of_property_read_bool(np, "oxsemi,ehci_use_pllb");
- oxnas->use_phya = of_property_read_bool(np, "oxsemi,ehci_use_phya");
-
- oxnas->syscon = syscon_regmap_lookup_by_phandle(np, "oxsemi,sys-ctrl");
- if (IS_ERR(oxnas->syscon)) {
- err = PTR_ERR(oxnas->syscon);
- goto err_syscon;
- }
-
- oxnas->clk = of_clk_get_by_name(np, "usb");
- if (IS_ERR(oxnas->clk)) {
- err = PTR_ERR(oxnas->clk);
- goto err_clk;
- }
-
- if (oxnas->use_pllb) {
- oxnas->refsrc = of_clk_get_by_name(np, "refsrc");
- if (IS_ERR(oxnas->refsrc)) {
- err = PTR_ERR(oxnas->refsrc);
- goto err_refsrc;
- }
- oxnas->phyref = of_clk_get_by_name(np, "phyref");
- if (IS_ERR(oxnas->refsrc)) {
- err = PTR_ERR(oxnas->refsrc);
- goto err_phyref;
- }
-
- } else {
- oxnas->refsrc = NULL;
- oxnas->phyref = NULL;
- }
-
- rstc = devm_reset_control_get(&ofdev->dev, "host");
- if (IS_ERR(rstc)) {
- err = PTR_ERR(rstc);
- goto err_rst;
- }
- oxnas->rst_host = rstc;
-
- rstc = devm_reset_control_get(&ofdev->dev, "phya");
- if (IS_ERR(rstc)) {
- err = PTR_ERR(rstc);
- goto err_rst;
- }
- oxnas->rst_phya = rstc;
-
- rstc = devm_reset_control_get(&ofdev->dev, "phyb");
- if (IS_ERR(rstc)) {
- err = PTR_ERR(rstc);
- goto err_rst;
- }
- oxnas->rst_phyb = rstc;
-
- irq = irq_of_parse_and_map(np, 0);
- if (!irq) {
- dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
- err = -EBUSY;
- goto err_irq;
- }
-
- hcd->has_tt = 1;
- ehci = hcd_to_ehci(hcd);
- ehci->caps = hcd->regs;
-
- start_oxnas_usb_ehci(oxnas);
-
- err = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (err)
- goto err_hcd;
-
- return 0;
-
-err_hcd:
- stop_oxnas_usb_ehci(oxnas);
-err_irq:
-err_rst:
- if (oxnas->phyref)
- clk_put(oxnas->phyref);
-err_phyref:
- if (oxnas->refsrc)
- clk_put(oxnas->refsrc);
-err_refsrc:
- clk_put(oxnas->clk);
-err_syscon:
-err_clk:
-err_ioremap:
-err_res:
- usb_put_hcd(hcd);
-
- return err;
-}
-
-static int ehci_oxnas_drv_remove(struct platform_device *pdev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
- struct oxnas_hcd *oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv;
-
- usb_remove_hcd(hcd);
- if (oxnas->use_pllb) {
- clk_disable_unprepare(oxnas->phyref);
- clk_put(oxnas->phyref);
- clk_disable_unprepare(oxnas->refsrc);
- clk_put(oxnas->refsrc);
- }
- clk_disable_unprepare(oxnas->clk);
- usb_put_hcd(hcd);
-
- return 0;
-}
-
-static const struct of_device_id oxnas_ehci_dt_ids[] = {
- { .compatible = "plxtech,nas782x-ehci" },
- { /* sentinel */ }
-};
-
-MODULE_DEVICE_TABLE(of, oxnas_ehci_dt_ids);
-
-static struct platform_driver ehci_oxnas_driver = {
- .probe = ehci_oxnas_drv_probe,
- .remove = ehci_oxnas_drv_remove,
- .shutdown = usb_hcd_platform_shutdown,
- .driver.name = "oxnas-ehci",
- .driver.of_match_table = oxnas_ehci_dt_ids,
-};
-
-static const struct ehci_driver_overrides oxnas_overrides __initconst = {
- .reset = ehci_oxnas_reset,
- .extra_priv_size = sizeof(struct oxnas_hcd),
-};
-
-static int __init ehci_oxnas_init(void)
-{
- if (usb_disabled())
- return -ENODEV;
-
- ehci_init_driver(&oxnas_hc_driver, &oxnas_overrides);
- return platform_driver_register(&ehci_oxnas_driver);
-}
-module_init(ehci_oxnas_init);
-
-static void __exit ehci_oxnas_cleanup(void)
-{
- platform_driver_unregister(&ehci_oxnas_driver);
-}
-module_exit(ehci_oxnas_cleanup);
-
-MODULE_DESCRIPTION(DRIVER_DESC);
-MODULE_ALIAS("platform:oxnas-ehci");
-MODULE_LICENSE("GPL");
+++ /dev/null
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux
-UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage
-
-include $(SUBTARGET).mk
-
-$(eval $(call BuildImage))
+++ /dev/null
-KERNEL_LOADADDR := 0x48008000
-
-define Device/Default
- KERNEL_NAME := zImage
- KERNEL_SUFFIX := -uImage
- KERNEL_INSTALL := 1
- FILESYSTEMS := squashfs ext4
- PROFILES := Default
- DEVICE_DTS := ox810se-$(subst _,-,$(1))
- IMAGES := sysupgrade.tar
- IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
-endef
-
-define Device/wd_mbwe
- DEVICE_VENDOR := Western Digital
- DEVICE_MODEL := My Book
- DEVICE_VARIANT := World Edition
- KERNEL := kernel-bin | append-dtb | uImage none
-endef
-TARGET_DEVICES += wd_mbwe
+++ /dev/null
-UBIFS_OPTS := -m 2048 -e 126KiB -c 4096
-KERNEL_LOADADDR := 0x60008000
-
-define Device/Default
- KERNEL_NAME := zImage
- KERNEL_SUFFIX := -uImage
- KERNEL_INSTALL := 1
- BLOCKSIZE := 128k
- PAGESIZE := 2048
- SUBPAGESIZE := 512
- FILESYSTEMS := squashfs ubifs
- PROFILES := Default
- DEVICE_DTS := ox820-$(subst _,-,$(1))
- KERNEL := kernel-bin | append-dtb | uImage none
- IMAGES := ubinized.bin sysupgrade.tar
- IMAGE/ubinized.bin := append-ubi
- IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
-endef
-
-define Build/omninas-factory
- mkimage -A arm -T ramdisk -C gzip -n "dummy" \
- $(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") .
-endef
-
-define Build/encrypt-3des
-endef
-
-define Device/akitio_mycloud
- DEVICE_VENDOR := Akitio
- DEVICE_MODEL := MyCloud Mini
- SUPPORTED_DEVICES += akitio
- DEVICE_PACKAGES := kmod-ata-oxnas-sata kmod-i2c-gpio kmod-rtc-ds1307 \
- kmod-usb2-oxnas kmod-usb-ledtrig-usbport
-endef
-TARGET_DEVICES += akitio_mycloud
-
-define Device/cloudengines_pogoplugpro
- DEVICE_VENDOR := Cloud Engines
- DEVICE_MODEL := PogoPlug Pro (with mPCIe)
- SUPPORTED_DEVICES += pogoplug-pro
- DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb-ledtrig-usbport \
- kmod-ata-oxnas-sata kmod-rt2800-pci wpad-basic-mbedtls
-endef
-TARGET_DEVICES += cloudengines_pogoplugpro
-
-define Device/cloudengines_pogoplug-series-3
- DEVICE_VENDOR := Cloud Engines
- DEVICE_MODEL := PogoPlug Series V3 (without mPCIe)
- SUPPORTED_DEVICES += cloudengines,pogoplugv3 pogoplug-v3
- DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb-ledtrig-usbport \
- kmod-ata-oxnas-sata
-endef
-TARGET_DEVICES += cloudengines_pogoplug-series-3
-
-define Device/shuttle_kd20
- DEVICE_VENDOR := Shuttle
- DEVICE_MODEL := KD20
- SUPPORTED_DEVICES += kd20
- DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb3 kmod-usb-ledtrig-usbport \
- kmod-i2c-gpio kmod-rtc-pcf8563 kmod-gpio-beeper kmod-hwmon-drivetemp \
- kmod-hwmon-gpiofan kmod-ata-oxnas-sata kmod-md-mod kmod-md-raid0 \
- kmod-md-raid1 kmod-fs-ext4 kmod-fs-xfs
-endef
-TARGET_DEVICES += shuttle_kd20
-
-define Device/mitrastar_stg-212
- DEVICE_VENDOR := MitraStar
- DEVICE_MODEL := STG-212
- SUPPORTED_DEVICES += stg212
- DEVICE_PACKAGES := kmod-ata-oxnas-sata kmod-fs-ext4 kmod-fs-xfs \
- kmod-usb2-oxnas kmod-usb-ledtrig-usbport
-endef
-TARGET_DEVICES += mitrastar_stg-212
+++ /dev/null
-define KernelPackage/ata-oxnas-sata
- TITLE:=oxnas Serial ATA support
- KCONFIG:=CONFIG_SATA_OXNAS
- FILES:=$(LINUX_DIR)/drivers/ata/sata_oxnas.ko
- AUTOLOAD:=$(call AutoLoad,41,sata_oxnas,1)
- $(call AddDepends/ata,@TARGET_oxnas)
-endef
-
-define KernelPackage/ata-oxnas-sata/description
- SATA support for OX934 core found in the OX8xx/PLX782x SoCs
-endef
-
-$(eval $(call KernelPackage,ata-oxnas-sata))
-
-
-define KernelPackage/usb2-oxnas
- TITLE:=OX820 EHCI driver
- KCONFIG:=CONFIG_USB_EHCI_OXNAS
- FILES:=$(LINUX_DIR)/drivers/usb/host/ehci-oxnas.ko
- AUTOLOAD:=$(call AutoLoad,55,ehci-oxnas,1)
- $(call AddDepends/usb,@TARGET_oxnas_ox820 +kmod-usb2)
-endef
-
-define KernelPackage/usb2-oxnas/description
- This driver provides USB Device Controller support for the
- EHCI USB host built-in to the OX820 SoC.
-endef
-
-$(eval $(call KernelPackage,usb2-oxnas))
+++ /dev/null
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-# CONFIG_DEBUG_UNCOMPRESS is not set
-CONFIG_EXT4_FS=y
-CONFIG_FS_MBCACHE=y
-CONFIG_MACH_OX810SE=y
+++ /dev/null
-define Profile/Default
- NAME:=Default Profile
- PRIORITY:=1
-endef
-
-define Profile/Default/Description
- Default package set compatible with most boards.
-endef
-
-$(eval $(call Profile,Default))
+++ /dev/null
-FEATURES+=source-only
-
-SUBTARGET:=ox810se
-BOARDNAME:=OX810SE
-CPU_TYPE:=arm926ej-s
-
-define Target/Description
- Oxford OX810SE
-endef
+++ /dev/null
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_WANT_LIBATA_LEDS=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ATA_LEDS=y
-CONFIG_CACHE_L2X0=y
-# CONFIG_CACHE_L2X0_PMU is not set
-CONFIG_CPU_32v6=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_ABRT_EV6=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V6=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_PABRT_V6=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V6=y
-CONFIG_CPU_V6K=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_LL_UART_8250=y
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
-CONFIG_DEBUG_UART_8250_SHIFT=0
-CONFIG_DEBUG_UART_PHYS=0x44200000
-CONFIG_DEBUG_UART_VIRT=0xf4200000
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_DMA_CACHE_RWFO=y
-CONFIG_FORCE_MAX_ZONEORDER=12
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_SMP=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MACH_OX820=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-# CONFIG_MTD_NAND_ECC_SW_BCH is not set
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
-CONFIG_MTD_NAND_OXNAS=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NR_CPUS=16
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_OXNAS=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-# CONFIG_PL310_ERRATA_753970 is not set
-# CONFIG_PL310_ERRATA_769419 is not set
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_SECURITY=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress-ox820.h"
-CONFIG_XPS=y
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# Copyright (C) 2016 OpenWrt.org
-
-define Profile/Default
- NAME:=Default Profile
- PRIORITY:=1
- PACKAGES:=\
- kmod-i2c-gpio kmod-gpio-beeper kmod-hwmon-gpiofan \
- kmod-rtc-pcf8563 kmod-rtc-ds1307 kmod-usb3
-endef
-
-define Profile/Default/Description
- Default package set compatible with most boards.
-endef
-
-$(eval $(call Profile,Default))
+++ /dev/null
-SUBTARGET:=ox820
-BOARDNAME:=OX820/NAS782x
-CPU_TYPE:=mpcore
-FEATURES+=nand pci pcie ubifs usb
-
-define Target/Description
- Oxford/PLXTECH OX820/NAS782x
-endef
\ No newline at end of file
+++ /dev/null
-- add compatible string
-- add console to bootargs
-- add led aliases
-- adjust nand partition table
----
---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-@@ -11,10 +11,10 @@
- / {
- model = "Cloud Engines PogoPlug Series 3";
-
-- compatible = "cloudengines,pogoplugv3", "oxsemi,ox820";
-+ compatible = "cloudengines,pogoplug-series-3", "cloudengines,pogoplugv3", "oxsemi,ox820";
-
- chosen {
-- bootargs = "earlyprintk";
-+ bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
-@@ -27,24 +27,28 @@
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
-+ led-boot = &led_status;
-+ led-failsafe = &led_warn;
-+ led-running = &led_act;
-+ led-upgrade = &led_warn;
- };
-
- leds {
- compatible = "gpio-leds";
-
-- blue {
-+ led_status: blue {
- label = "pogoplug:blue";
- gpios = <&gpio0 2 0>;
- default-state = "keep";
- };
-
-- orange {
-+ led_warn: orange {
- label = "pogoplug:orange";
- gpios = <&gpio1 16 1>;
- default-state = "keep";
- };
-
-- green {
-+ led_act: green {
- label = "pogoplug:green";
- gpios = <&gpio1 17 1>;
- default-state = "keep";
-@@ -73,11 +77,27 @@
- nand-ecc-algo = "hamming";
-
- partition@0 {
-- label = "boot";
-- reg = <0x00000000 0x00e00000>;
-+ label = "stage1";
-+ reg = <0x00000000 0x00040000>;
- read-only;
- };
-
-+ partition@40000 {
-+ label = "u-boot";
-+ reg = <0x00040000 0x00380000>;
-+ read-only;
-+ };
-+
-+ partition@3c0000 {
-+ label = "u-boot-env";
-+ reg = <0x003c0000 0x00080000>;
-+ };
-+
-+ partition@440000 {
-+ label = "kernel";
-+ reg = <0x00440000 0x009c0000>;
-+ };
-+
- partition@e00000 {
- label = "ubi";
- reg = <0x00e00000 0x07200000>;
+++ /dev/null
-From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001
-Date: Fri, 1 Jun 2018 02:41:15 +0200
-Subject: [PATCH] arm: ox820: remove left-overs
-
----
- drivers/clk/clk-oxnas.c | 2 --
- include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++-------------
- 2 files changed, 14 insertions(+), 20 deletions(-)
-
---- a/drivers/clk/clk-oxnas.c
-+++ b/drivers/clk/clk-oxnas.c
-@@ -29,8 +29,6 @@ struct oxnas_stdclk_data {
- struct clk_hw_onecell_data *onecell_data;
- struct clk_oxnas_gate **gates;
- unsigned int ngates;
-- struct clk_oxnas_pll **plls;
-- unsigned int nplls;
- };
-
- /* Regmap offsets */
---- a/include/dt-bindings/clock/oxsemi,ox820.h
-+++ b/include/dt-bindings/clock/oxsemi,ox820.h
-@@ -6,24 +6,20 @@
- #ifndef DT_CLOCK_OXSEMI_OX820_H
- #define DT_CLOCK_OXSEMI_OX820_H
-
--/* PLLs */
--#define CLK_820_PLLA 0
--#define CLK_820_PLLB 1
--
- /* Gate Clocks */
--#define CLK_820_LEON 2
--#define CLK_820_DMA_SGDMA 3
--#define CLK_820_CIPHER 4
--#define CLK_820_SD 5
--#define CLK_820_SATA 6
--#define CLK_820_AUDIO 7
--#define CLK_820_USBMPH 8
--#define CLK_820_ETHA 9
--#define CLK_820_PCIEA 10
--#define CLK_820_NAND 11
--#define CLK_820_PCIEB 12
--#define CLK_820_ETHB 13
--#define CLK_820_REF600 14
--#define CLK_820_USBDEV 15
-+#define CLK_820_LEON 0
-+#define CLK_820_DMA_SGDMA 1
-+#define CLK_820_CIPHER 2
-+#define CLK_820_SD 3
-+#define CLK_820_SATA 4
-+#define CLK_820_AUDIO 5
-+#define CLK_820_USBMPH 6
-+#define CLK_820_ETHA 7
-+#define CLK_820_PCIEA 8
-+#define CLK_820_NAND 9
-+#define CLK_820_PCIEB 10
-+#define CLK_820_ETHB 11
-+#define CLK_820_REF600 12
-+#define CLK_820_USBDEV 13
-
- #endif /* DT_CLOCK_OXSEMI_OX820_H */
+++ /dev/null
---- a/drivers/clk/clk-oxnas.c
-+++ b/drivers/clk/clk-oxnas.c
-@@ -5,19 +5,42 @@
- */
-
-+#include <linux/clk.h>
-+#include <linux/clkdev.h>
- #include <linux/clk-provider.h>
- #include <linux/kernel.h>
- #include <linux/init.h>
-+#include <linux/delay.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
- #include <linux/platform_device.h>
- #include <linux/stringify.h>
- #include <linux/regmap.h>
- #include <linux/mfd/syscon.h>
-+#include <linux/reset.h>
-
- #include <dt-bindings/clock/oxsemi,ox810se.h>
- #include <dt-bindings/clock/oxsemi,ox820.h>
-
-+#define REF300_DIV_INT_SHIFT 8
-+#define REF300_DIV_FRAC_SHIFT 0
-+#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
-+#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
-+
-+#define PLLB_BYPASS 1
-+#define PLLB_ENSAT 3
-+#define PLLB_OUTDIV 4
-+#define PLLB_REFDIV 8
-+#define PLLB_DIV_INT_SHIFT 8
-+#define PLLB_DIV_FRAC_SHIFT 0
-+#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
-+#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
-+
-+#define PLLA_REFDIV_MASK 0x3F
-+#define PLLA_REFDIV_SHIFT 8
-+#define PLLA_OUTDIV_MASK 0x7
-+#define PLLA_OUTDIV_SHIFT 4
-+
- /* Standard regmap gate clocks */
- struct clk_oxnas_gate {
- struct clk_hw hw;
-@@ -36,6 +59,135 @@ struct oxnas_stdclk_data {
- #define CLK_SET_REGOFFSET 0x2c
- #define CLK_CLR_REGOFFSET 0x30
-
-+#define PLLA_CTRL0_REGOFFSET 0x1f0
-+#define PLLA_CTRL1_REGOFFSET 0x1f4
-+#define PLLB_CTRL0_REGOFFSET 0x1001f0
-+#define MHZ (1000 * 1000)
-+
-+struct clk_oxnas_pll {
-+ struct clk_hw hw;
-+ struct device_node *devnode;
-+ struct reset_control *rstc;
-+ struct regmap *syscon;
-+};
-+
-+#define to_clk_oxnas_pll(_hw) container_of(_hw, struct clk_oxnas_pll, hw)
-+
-+static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ struct clk_oxnas_pll *plla = to_clk_oxnas_pll(hw);
-+ unsigned long fin = parent_rate;
-+ unsigned long refdiv, outdiv;
-+ unsigned int pll0, fbdiv;
-+
-+ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL0_REGOFFSET, &pll0));
-+
-+ refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;
-+ refdiv += 1;
-+ outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;
-+ outdiv += 1;
-+
-+ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL1_REGOFFSET, &fbdiv));
-+ /* seems we will not be here when pll is bypassed, so ignore this
-+ * case */
-+
-+ return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;
-+}
-+
-+static const char *pll_clk_parents[] = {
-+ "oscillator",
-+};
-+
-+static struct clk_ops plla_ops = {
-+ .recalc_rate = plla_clk_recalc_rate,
-+};
-+
-+static struct clk_init_data clk_plla_init = {
-+ .name = "plla",
-+ .ops = &plla_ops,
-+ .parent_names = pll_clk_parents,
-+ .num_parents = ARRAY_SIZE(pll_clk_parents),
-+};
-+
-+static int pllb_clk_is_prepared(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ return !!pllb->rstc;
-+}
-+
-+static int pllb_clk_prepare(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ pllb->rstc = of_reset_control_get(pllb->devnode, NULL);
-+
-+ return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0;
-+}
-+
-+static void pllb_clk_unprepare(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ BUG_ON(IS_ERR(pllb->rstc));
-+
-+ reset_control_put(pllb->rstc);
-+ pllb->rstc = NULL;
-+}
-+
-+static int pllb_clk_enable(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ BUG_ON(IS_ERR(pllb->rstc));
-+
-+ /* put PLL into bypass */
-+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
-+ wmb();
-+ udelay(10);
-+ reset_control_assert(pllb->rstc);
-+ udelay(10);
-+ /* set PLL B control information */
-+ regmap_write_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, 0xffff,
-+ (1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV));
-+ reset_control_deassert(pllb->rstc);
-+ udelay(100);
-+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), 0);
-+
-+ return 0;
-+}
-+
-+static void pllb_clk_disable(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ BUG_ON(IS_ERR(pllb->rstc));
-+
-+ /* put PLL into bypass */
-+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
-+
-+ wmb();
-+ udelay(10);
-+
-+ reset_control_assert(pllb->rstc);
-+}
-+
-+static struct clk_ops pllb_ops = {
-+ .prepare = pllb_clk_prepare,
-+ .unprepare = pllb_clk_unprepare,
-+ .is_prepared = pllb_clk_is_prepared,
-+ .enable = pllb_clk_enable,
-+ .disable = pllb_clk_disable,
-+};
-+
-+static struct clk_init_data clk_pllb_init = {
-+ .name = "pllb",
-+ .ops = &pllb_ops,
-+ .parent_names = pll_clk_parents,
-+ .num_parents = ARRAY_SIZE(pll_clk_parents),
-+};
-+
- static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
- {
- return container_of(hw, struct clk_oxnas_gate, hw);
-@@ -251,3 +403,42 @@ static struct platform_driver oxnas_stdc
- },
- };
- builtin_platform_driver(oxnas_stdclk_driver);
-+
-+void __init oxnas_init_plla(struct device_node *np)
-+{
-+ struct clk *clk;
-+ struct clk_oxnas_pll *plla;
-+
-+ plla = kmalloc(sizeof(*plla), GFP_KERNEL);
-+ BUG_ON(!plla);
-+
-+ plla->syscon = syscon_node_to_regmap(of_get_parent(np));
-+ plla->hw.init = &clk_plla_init;
-+ plla->devnode = np;
-+ plla->rstc = NULL;
-+ clk = clk_register(NULL, &plla->hw);
-+ BUG_ON(IS_ERR(clk));
-+ /* mark it as enabled */
-+ clk_prepare_enable(clk);
-+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
-+}
-+CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla);
-+
-+void __init oxnas_init_pllb(struct device_node *np)
-+{
-+ struct clk *clk;
-+ struct clk_oxnas_pll *pllb;
-+
-+ pllb = kmalloc(sizeof(*pllb), GFP_KERNEL);
-+ BUG_ON(!pllb);
-+
-+ pllb->syscon = syscon_node_to_regmap(of_get_parent(np));
-+ pllb->hw.init = &clk_pllb_init;
-+ pllb->devnode = np;
-+ pllb->rstc = NULL;
-+
-+ clk = clk_register(NULL, &pllb->hw);
-+ BUG_ON(IS_ERR(clk));
-+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
-+}
-+CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb);
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -61,12 +61,6 @@
- clocks = <&osc>;
- };
-
-- plla: plla {
-- compatible = "fixed-clock";
-- #clock-cells = <0>;
-- clock-frequency = <850000000>;
-- };
--
- armclk: armclk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
-@@ -266,6 +260,19 @@
- compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
- #clock-cells = <1>;
- };
-+
-+ plla: plla {
-+ compatible = "plxtech,nas782x-plla";
-+ #clock-cells = <0>;
-+ clocks = <&osc>;
-+ };
-+
-+ pllb: pllb {
-+ compatible = "plxtech,nas782x-pllb";
-+ #clock-cells = <0>;
-+ clocks = <&osc>;
-+ resets = <&reset RESET_PLLB>;
-+ };
- };
- };
-
-@@ -287,6 +294,13 @@
- clocks = <&armclk>;
- };
-
-+ watchdog@620 {
-+ compatible = "mpcore_wdt";
-+ reg = <0x620 0x20>;
-+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
-+ clocks = <&armclk>;
-+ };
-+
- gic: interrupt-controller@1000 {
- compatible = "arm,arm11mp-gic";
- interrupt-controller;
+++ /dev/null
---- a/drivers/power/reset/Kconfig
-+++ b/drivers/power/reset/Kconfig
-@@ -148,6 +148,12 @@ config POWER_RESET_OXNAS
- help
- Restart support for OXNAS/PLXTECH OX820 SoC.
-
-+config POWER_RESET_OXNAS
-+ bool "OXNAS SoC restart driver"
-+ depends on ARCH_OXNAS
-+ help
-+ Restart support for OXNAS boards.
-+
- config POWER_RESET_PIIX4_POWEROFF
- tristate "Intel PIIX4 power-off driver"
- depends on PCI
---- a/drivers/power/reset/Makefile
-+++ b/drivers/power/reset/Makefile
-@@ -19,6 +19,7 @@ obj-$(CONFIG_POWER_RESET_QCOM_PON) += qc
- obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o
- obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
- obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
-+obj-$(CONFIG_POWER_RESET_OXNAS) += oxnas-restart.o
- obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
- obj-$(CONFIG_POWER_RESET_REGULATOR) += regulator-poweroff.o
- obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
+++ /dev/null
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -247,6 +247,15 @@
- };
- };
-
-+ pcie_phy: pcie-phy@a00000 {
-+ compatible = "oxsemi,ox820-pcie-phy";
-+ reg = <0xa00000 0x10>;
-+ #phy-cells = <0>;
-+ resets = <&reset RESET_PCIEPHY>;
-+ reset-names = "phy";
-+ status = "disabled";
-+ };
-+
- sys: sys-ctrl@e00000 {
- compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
- reg = <0xe00000 0x200000>;
---- a/drivers/phy/Kconfig
-+++ b/drivers/phy/Kconfig
-@@ -35,6 +35,13 @@ config PHY_LPC18XX_USB_OTG
- This driver is need for USB0 support on LPC18xx/43xx and takes
- care of enabling and clock setup.
-
-+config PHY_OXNAS
-+ tristate "Oxford Semi. OX820 PCI-E PHY support"
-+ depends on HAS_IOMEM && OF && (ARM || COMPILE_TEST)
-+ select GENERIC_PHY
-+ help
-+ This option enables support for OXNAS OX820 SoC PCIE PHY.
-+
- config PHY_PISTACHIO_USB
- tristate "IMG Pistachio USB2.0 PHY driver"
- depends on MIPS || COMPILE_TEST
---- a/drivers/phy/Makefile
-+++ b/drivers/phy/Makefile
-@@ -7,6 +7,7 @@ obj-$(CONFIG_GENERIC_PHY) += phy-core.o
- obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
- obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
- obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
-+obj-$(CONFIG_PHY_OXNAS) += phy-oxnas-pcie.o
- obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
- obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
- obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
+++ /dev/null
---- a/drivers/pci/controller/Kconfig
-+++ b/drivers/pci/controller/Kconfig
-@@ -312,6 +312,11 @@ config PCIE_HISI_ERR
- Say Y here if you want error handling support
- for the PCIe controller's errors on HiSilicon HIP SoCs
-
-+config PCIE_OXNAS
-+ bool "PLX Oxnas PCIe controller"
-+ depends on ARCH_OXNAS
-+ select PCIEPORTBUS
-+
- source "drivers/pci/controller/dwc/Kconfig"
- source "drivers/pci/controller/mobiveil/Kconfig"
- source "drivers/pci/controller/cadence/Kconfig"
---- a/drivers/pci/controller/Makefile
-+++ b/drivers/pci/controller/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie
- obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
- obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
- obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o
-+obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o
- obj-$(CONFIG_VMD) += vmd.o
- obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
- obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -289,7 +289,7 @@
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-- ranges = <0 0x47000000 0x1000000>;
-+ ranges = <0 0x47000000 0x2000>;
-
- scu: scu@0 {
- compatible = "arm,arm11mp-scu";
-@@ -318,5 +318,86 @@
- <0x100 0x500>;
- };
- };
-+
-+ pcie0: pcie@47c00000 {
-+ compatible = "plxtech,nas782x-pcie";
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ /* flag & space bus address host address size */
-+ ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000
-+ 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000
-+ 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000
-+ 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>;
-+
-+ bus-range = <0x00 0x7f>;
-+
-+ /* cfg inbound translator */
-+ reg = <0x47c00000 0x1000>, <0x47d00000 0x100>;
-+
-+ phys = <&pcie_phy>;
-+ phy-names = "pcie-phy";
-+
-+ #interrupt-cells = <1>;
-+ /* wild card mask, match all bus address & interrupt specifier */
-+ /* format: bus address mask, interrupt specifier mask */
-+ /* each bit 1 means need match, 0 means ignored when match */
-+ interrupt-map-mask = <0 0 0 0>;
-+ /* format: a list of: bus address, interrupt specifier,
-+ * parent interrupt controller & specifier */
-+ interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
-+ gpios = <&gpio1 12 0>;
-+ clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
-+ clock-names = "pcie", "busclk";
-+ resets = <&reset RESET_PCIEA>;
-+ reset-names = "pcie";
-+
-+ plxtech,pcie-hcsl-bit = <2>;
-+ plxtech,pcie-ctrl-offset = <0x120>;
-+ plxtech,pcie-outbound-offset = <0x138>;
-+ status = "disabled";
-+ };
-+
-+ pcie1: pcie@47e00000 {
-+ compatible = "plxtech,nas782x-pcie";
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ /* flag & space bus address host address size */
-+ ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000
-+ 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000
-+ 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000
-+ 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>;
-+
-+ bus-range = <0x80 0xff>;
-+
-+ /* cfg inbound translator */
-+ reg = <0x47e00000 0x1000>, <0x47f00000 0x100>;
-+
-+ phys = <&pcie_phy>;
-+ phy-names = "pcie-phy";
-+
-+ #interrupt-cells = <1>;
-+ /* wild card mask, match all bus address & interrupt specifier */
-+ /* format: bus address mask, interrupt specifier mask */
-+ /* each bit 1 means need match, 0 means ignored when match */
-+ interrupt-map-mask = <0 0 0 0>;
-+ /* format: a list of: bus address, interrupt specifier,
-+ * parent interrupt controller & specifier */
-+ interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
-+
-+ /* gpios = <&gpio1 12 0>; */
-+ clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
-+ clock-names = "pcie", "busclk";
-+ resets = <&reset RESET_PCIEB>;
-+ reset-names = "pcie";
-+
-+ plxtech,pcie-hcsl-bit = <3>;
-+ plxtech,pcie-ctrl-offset = <0x124>;
-+ plxtech,pcie-outbound-offset = <0x174>;
-+ status = "disabled";
-+ };
- };
- };
+++ /dev/null
---- a/drivers/ata/Kconfig
-+++ b/drivers/ata/Kconfig
-@@ -568,6 +568,14 @@ config SATA_VITESSE
-
- If unsure, say N.
-
-+config SATA_OXNAS
-+ tristate "PLXTECH NAS782X SATA support"
-+ select SATA_HOST
-+ help
-+ This option enables support for Nas782x Serial ATA controller.
-+
-+ If unsure, say N.
-+
- comment "PATA SFF controllers with BMDMA"
-
- config PATA_ALI
---- a/drivers/ata/Makefile
-+++ b/drivers/ata/Makefile
-@@ -46,6 +46,7 @@ obj-$(CONFIG_SATA_SVW) += sata_svw.o
- obj-$(CONFIG_SATA_ULI) += sata_uli.o
- obj-$(CONFIG_SATA_VIA) += sata_via.o
- obj-$(CONFIG_SATA_VITESSE) += sata_vsc.o
-+obj-$(CONFIG_SATA_OXNAS) += sata_oxnas.o
-
- # SFF PATA w/ BMDMA
- obj-$(CONFIG_PATA_ALI) += pata_ali.o
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -399,5 +399,20 @@
- plxtech,pcie-outbound-offset = <0x174>;
- status = "disabled";
- };
-+
-+ sata: sata@45900000 {
-+ compatible = "plxtech,nas782x-sata";
-+ /* ports dmactl sgdma */
-+ reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>,
-+ /* core phy descriptors (optional) */
-+ <0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>;
-+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&stdclk CLK_820_SATA>;
-+ resets = <&reset RESET_SATA>, <&reset RESET_SATA_LINK>, <&reset RESET_SATA_PHY>;
-+ reset-names = "sata", "link", "phy";
-+ nr-ports = <1>;
-+ status = "disabled";
-+ };
-+
- };
- };
---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-@@ -111,3 +111,7 @@
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
- };
-+
-+&sata {
-+ status = "okay";
-+};
+++ /dev/null
---- a/arch/arm/mach-oxnas/Kconfig
-+++ b/arch/arm/mach-oxnas/Kconfig
-@@ -2,6 +2,7 @@
- menuconfig ARCH_OXNAS
- bool "Oxford Semiconductor OXNAS Family SoCs"
- select ARCH_HAS_RESET_CONTROLLER
-+ select ARCH_WANT_LIBATA_LEDS
- select COMMON_CLK_OXNAS
- select GPIOLIB
- select MFD_SYSCON
+++ /dev/null
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -339,6 +339,13 @@ config USB_OCTEON_EHCI
- USB 2.0 device support. All CN6XXX based chips with USB are
- supported.
-
-+config USB_EHCI_OXNAS
-+ tristate "OXNAS EHCI Module"
-+ depends on USB_EHCI_HCD && ARCH_OXNAS
-+ select USB_EHCI_ROOT_HUB_TT
-+ help
-+ Enable support for the OX820 SOC's on-chip EHCI controller.
-+
- endif # USB_EHCI_HCD
-
- config USB_OXU210HP_HCD
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -46,6 +46,7 @@ obj-$(CONFIG_USB_EHCI_HCD_STI) += ehci-s
- obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
- obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o
- obj-$(CONFIG_USB_EHCI_BRCMSTB) += ehci-brcm.o
-+obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o
-
- obj-$(CONFIG_USB_OXU210HP_HCD) += oxu210hp-hcd.o
- obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -106,6 +106,31 @@
- status = "disabled";
- };
-
-+ ehci: ehci@40200100 {
-+ compatible = "plxtech,nas782x-ehci";
-+ reg = <0x40200100 0xf00>;
-+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&stdclk CLK_820_USBMPH>, <&pllb>, <&stdclk CLK_820_REF600>;
-+ clock-names = "usb", "refsrc", "phyref";
-+ resets = <&reset RESET_USBHS>, <&reset RESET_USBPHYA>, <&reset RESET_USBPHYB>;
-+ reset-names = "host", "phya", "phyb";
-+ oxsemi,sys-ctrl = <&sys>;
-+ /* Otherwise ref300 is used, which is derived from sata phy
-+ * in that case, usb depends on sata initialization */
-+ /* FIXME: how to make this dependency explicit ? */
-+ oxsemi,ehci_use_pllb;
-+ status = "disabled";
-+
-+ ehci_port1: port@1 {
-+ reg = <1>;
-+ #trigger-source-cells = <0>;
-+ };
-+ ehci_port2: port@2 {
-+ reg = <2>;
-+ #trigger-source-cells = <0>;
-+ };
-+ };
-+
- apb-bridge@44000000 {
- #address-cells = <1>;
- #size-cells = <1>;
---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-@@ -105,6 +105,10 @@
- };
- };
-
-+&ehci {
-+ status = "okay";
-+};
-+
- ða {
- status = "okay";
-
+++ /dev/null
-From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
-Date: Thu, 9 Mar 2017 09:37:17 +0100
-Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
-
-The command-line arguments provided by the boot loader will be
-appended to a new device tree property: bootloader-args.
-If there is a property "append-rootblock" in DT under /chosen
-and a root= option in bootloaders command line it will be parsed
-and added to DT bootargs with the form: <append-rootblock>XX.
-Only command line ATAG will be processed, the rest of the ATAGs
-sent by bootloader will be ignored.
-This is usefull in dual boot systems, to get the current root partition
-without afecting the rest of the system.
-
----
- arch/arm/Kconfig | 11 +++++
- arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++-
- init/main.c | 16 ++++++++
- 3 files changed, 98 insertions(+), 1 deletion(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1728,6 +1728,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- The command-line arguments provided by the boot loader will be
- appended to the the device tree bootargs property.
-
-+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+ bool "Append rootblock parsing bootloader's kernel arguments"
-+ help
-+ The command-line arguments provided by the boot loader will be
-+ appended to a new device tree property: bootloader-args.
-+ If there is a property "append-rootblock" in DT under /chosen
-+ and a root= option in bootloaders command line it will be parsed
-+ and added to DT bootargs with the form: <append-rootblock>XX.
-+ Only command line ATAG will be processed, the rest of the ATAGs
-+ sent by bootloader will be ignored.
-+
- endchoice
-
- config CMDLINE
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -5,6 +5,8 @@
-
- #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
- #define do_extend_cmdline 1
-+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#define do_extend_cmdline 1
- #else
- #define do_extend_cmdline 0
- #endif
-@@ -20,6 +22,7 @@ static int node_offset(void *fdt, const
- return offset;
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop(void *fdt, const char *node_path, const char *property,
- void *val_array, int size)
- {
-@@ -28,6 +31,7 @@ static int setprop(void *fdt, const char
- return offset;
- return fdt_setprop(fdt, offset, property, val_array, size);
- }
-+#endif
-
- static int setprop_string(void *fdt, const char *node_path,
- const char *property, const char *string)
-@@ -38,6 +42,7 @@ static int setprop_string(void *fdt, con
- return fdt_setprop_string(fdt, offset, property, string);
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop_cell(void *fdt, const char *node_path,
- const char *property, uint32_t val)
- {
-@@ -46,6 +51,7 @@ static int setprop_cell(void *fdt, const
- return offset;
- return fdt_setprop_cell(fdt, offset, property, val);
- }
-+#endif
-
- static const void *getprop(const void *fdt, const char *node_path,
- const char *property, int *len)
-@@ -58,6 +64,7 @@ static const void *getprop(const void *f
- return fdt_getprop(fdt, offset, property, len);
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static uint32_t get_cell_size(const void *fdt)
- {
- int len;
-@@ -69,6 +76,61 @@ static uint32_t get_cell_size(const void
- return cell_size;
- }
-
-+#endif
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+
-+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
-+{
-+ const char *ptr, *end;
-+ const char *root="root=";
-+ int i, l;
-+ const char *rootblock;
-+
-+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
-+ ptr = str - 1;
-+
-+ do {
-+ //first find an 'r' at the begining or after a space
-+ do {
-+ ptr++;
-+ ptr = strchr(ptr, 'r');
-+ if(!ptr) return dest;
-+
-+ } while (ptr != str && *(ptr-1) != ' ');
-+
-+ //then check for the rest
-+ for(i = 1; i <= 4; i++)
-+ if(*(ptr+i) != *(root+i)) break;
-+
-+ } while (i != 5);
-+
-+ end = strchr(ptr, ' ');
-+ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
-+
-+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
-+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
-+ ptr = end + 1;
-+
-+ /* if append-rootblock property is set use it to append to command line */
-+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
-+ if(rootblock != NULL) {
-+ if(*dest != ' ') {
-+ *dest = ' ';
-+ dest++;
-+ len++;
-+ }
-+ if (len + l + i <= COMMAND_LINE_SIZE) {
-+ memcpy(dest, rootblock, l);
-+ dest += l - 1;
-+ memcpy(dest, ptr, i);
-+ dest += i;
-+ }
-+ }
-+ return dest;
-+}
-+#endif
-+
- static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
- {
- char cmdline[COMMAND_LINE_SIZE];
-@@ -88,18 +150,28 @@ static void merge_fdt_bootargs(void *fdt
-
- /* and append the ATAG_CMDLINE */
- if (fdt_cmdline) {
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+ //save original bootloader args
-+ //and append ubi.mtd with root partition number to current cmdline
-+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
-+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
-+
-+#else
- len = strlen(fdt_cmdline);
- if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
- *ptr++ = ' ';
- memcpy(ptr, fdt_cmdline, len);
- ptr += len;
- }
-+#endif
- }
- *ptr = '\0';
-
- setprop_string(fdt, "/chosen", "bootargs", cmdline);
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static void hex_str(char *out, uint32_t value)
- {
- uint32_t digit;
-@@ -117,6 +189,7 @@ static void hex_str(char *out, uint32_t
- }
- *out = '\0';
- }
-+#endif
-
- /*
- * Convert and fold provided ATAGs into the provided FDT.
-@@ -131,9 +204,11 @@ int atags_to_fdt(void *atag_list, void *
- struct tag *atag = atag_list;
- /* In the case of 64 bits memory size, need to reserve 2 cells for
- * address and size for each bank */
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- __be32 mem_reg_property[2 * 2 * NR_BANKS];
-- int memcount = 0;
-- int ret, memsize;
-+ int memsize, memcount = 0;
-+#endif
-+ int ret;
-
- /* make sure we've got an aligned pointer */
- if ((u32)atag_list & 0x3)
-@@ -168,7 +243,9 @@ int atags_to_fdt(void *atag_list, void *
- else
- setprop_string(fdt, "/chosen", "bootargs",
- atag->u.cmdline.cmdline);
-- } else if (atag->hdr.tag == ATAG_MEM) {
-+ }
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+ else if (atag->hdr.tag == ATAG_MEM) {
- if (memcount >= sizeof(mem_reg_property)/4)
- continue;
- if (!atag->u.mem.size)
-@@ -212,6 +289,10 @@ int atags_to_fdt(void *atag_list, void *
- setprop(fdt, "/memory", "reg", mem_reg_property,
- 4 * memcount * memsize);
- }
-+#else
-+
-+ }
-+#endif
-
- return fdt_pack(fdt);
- }
---- a/init/main.c
-+++ b/init/main.c
-@@ -113,6 +113,10 @@
-
- #include <kunit/test.h>
-
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#include <linux/of.h>
-+#endif
-+
- static int kernel_init(void *);
-
- extern void init_IRQ(void);
-@@ -993,6 +997,18 @@ asmlinkage __visible void __init __no_sa
- page_alloc_init();
-
- pr_notice("Kernel command line: %s\n", saved_command_line);
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+ //Show bootloader's original command line for reference
-+ if(of_chosen) {
-+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
-+ if(prop)
-+ pr_notice("Bootloader command line (ignored): %s\n", prop);
-+ else
-+ pr_notice("Bootloader command line not present\n");
-+ }
-+#endif
-+
- /* parameters may set static keys */
- jump_label_init();
- parse_early_param();
+++ /dev/null
---- a/drivers/ata/libata-core.c
-+++ b/drivers/ata/libata-core.c
-@@ -1531,6 +1531,14 @@ unsigned ata_exec_internal_sg(struct ata
- return AC_ERR_SYSTEM;
- }
-
-+ if (ap->ops->acquire_hw && !ap->ops->acquire_hw(ap, 0, 0)) {
-+ spin_unlock_irqrestore(ap->lock, flags);
-+ if (!ap->ops->acquire_hw(ap, 1, (2*HZ))) {
-+ return AC_ERR_TIMEOUT;
-+ }
-+ spin_lock_irqsave(ap->lock, flags);
-+ }
-+
- /* initialize internal qc */
- qc = __ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
-
-@@ -4587,6 +4595,9 @@ struct ata_queued_cmd *ata_qc_new_init(s
- if (unlikely(ap->pflags & ATA_PFLAG_FROZEN))
- return NULL;
-
-+ if (ap->ops->qc_new && ap->ops->qc_new(ap))
-+ return NULL;
-+
- /* libsas case */
- if (ap->flags & ATA_FLAG_SAS_HOST) {
- tag = ata_sas_allocate_tag(ap);
-@@ -4632,6 +4643,8 @@ void ata_qc_free(struct ata_queued_cmd *
- qc->tag = ATA_TAG_POISON;
- if (ap->flags & ATA_FLAG_SAS_HOST)
- ata_sas_free_tag(tag, ap);
-+ if (ap->ops->qc_free)
-+ ap->ops->qc_free(qc);
- }
- }
-
---- a/include/linux/libata.h
-+++ b/include/linux/libata.h
-@@ -927,6 +927,8 @@ struct ata_port_operations {
- enum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *qc);
- unsigned int (*qc_issue)(struct ata_queued_cmd *qc);
- bool (*qc_fill_rtf)(struct ata_queued_cmd *qc);
-+ int (*qc_new)(struct ata_port *ap);
-+ void (*qc_free)(struct ata_queued_cmd *qc);
-
- /*
- * Configuration and exception handling
-@@ -1017,6 +1019,9 @@ struct ata_port_operations {
- void (*phy_reset)(struct ata_port *ap);
- void (*eng_timeout)(struct ata_port *ap);
-
-+ int (*acquire_hw)(struct ata_port *ap, int may_sleep,
-+ int timeout_jiffies);
-+
- /*
- * ->inherits must be the last field and all the preceding
- * fields must be pointers.
projects / openwrt / staging / ansuel.git / commitdiff