--- /dev/null
+From 17d4f2a9e6cb224012d85fed52e9794a84fa501d Mon Sep 17 00:00:00 2001
+Date: Tue, 2 Sep 2025 13:59:13 +0200
+Subject: [PATCH 1/1] pinctrl: airoha: replace struct function_desc with struct
+ pinfunction
+
+struct function_desc is a wrapper around struct pinfunction with an
+additional void *data pointer. This driver doesn't use the data pointer.
+We're also working towards reducing the usage of struct function_desc in
+pinctrl drivers - they should only be created by pinmux core and
+accessed by drivers using pinmux_generic_get_function(). Replace the
+struct function_desc objects in this driver with smaller struct
+pinfunction instances.
+
+---
+ drivers/pinctrl/mediatek/pinctrl-airoha.c | 15 +++++----------
+ 1 file changed, 5 insertions(+), 10 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
++++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+@@ -35,13 +35,8 @@
+
+ #define PINCTRL_FUNC_DESC(id) \
+ { \
+- .desc = { \
+- .func = { \
+- .name = #id, \
+- .groups = id##_groups, \
+- .ngroups = ARRAY_SIZE(id##_groups), \
+- } \
+- }, \
++ .desc = PINCTRL_PINFUNCTION(#id, id##_groups, \
++ ARRAY_SIZE(id##_groups)), \
+ .groups = id##_func_group, \
+ .group_size = ARRAY_SIZE(id##_func_group), \
+ }
+@@ -334,7 +329,7 @@ struct airoha_pinctrl_func_group {
+ };
+
+ struct airoha_pinctrl_func {
+- const struct function_desc desc;
++ const struct pinfunction desc;
+ const struct airoha_pinctrl_func_group *groups;
+ u8 group_size;
+ };
+@@ -2911,13 +2906,13 @@ static int airoha_pinctrl_probe(struct p
+
+ func = &airoha_pinctrl_funcs[i];
+ err = pinmux_generic_add_function(pinctrl->ctrl,
+- func->desc.func.name,
+- func->desc.func.groups,
+- func->desc.func.ngroups,
++ func->desc.name,
++ func->desc.groups,
++ func->desc.ngroups,
+ (void *)func);
+ if (err < 0) {
+ dev_err(dev, "Failed to register function %s\n",
+- func->desc.func.name);
++ func->desc.name);
+ return err;
+ }
+ }
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
-@@ -1752,8 +1752,8 @@ static const struct airoha_pinctrl_func_
+@@ -1747,8 +1747,8 @@ static const struct airoha_pinctrl_func_
.regmap[0] = {
AIROHA_FUNC_MUX,
REG_GPIO_2ND_I2C_MODE,
},
.regmap[1] = {
AIROHA_FUNC_MUX,
-@@ -1816,8 +1816,8 @@ static const struct airoha_pinctrl_func_
+@@ -1811,8 +1811,8 @@ static const struct airoha_pinctrl_func_
.regmap[0] = {
AIROHA_FUNC_MUX,
REG_GPIO_2ND_I2C_MODE,
},
.regmap[1] = {
AIROHA_FUNC_MUX,
-@@ -1880,8 +1880,8 @@ static const struct airoha_pinctrl_func_
+@@ -1875,8 +1875,8 @@ static const struct airoha_pinctrl_func_
.regmap[0] = {
AIROHA_FUNC_MUX,
REG_GPIO_2ND_I2C_MODE,
},
.regmap[1] = {
AIROHA_FUNC_MUX,
-@@ -1944,8 +1944,8 @@ static const struct airoha_pinctrl_func_
+@@ -1939,8 +1939,8 @@ static const struct airoha_pinctrl_func_
.regmap[0] = {
AIROHA_FUNC_MUX,
REG_GPIO_2ND_I2C_MODE,
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
-@@ -108,6 +108,9 @@
+@@ -103,6 +103,9 @@
#define JTAG_UDI_EN_MASK BIT(4)
#define JTAG_DFD_EN_MASK BIT(3)
/* LED MAP */
#define REG_LAN_LED0_MAPPING 0x027c
#define REG_LAN_LED1_MAPPING 0x0280
-@@ -719,16 +722,16 @@ static const struct airoha_pinctrl_func_
+@@ -714,16 +717,16 @@ static const struct airoha_pinctrl_func_
.name = "mdio",
.regmap[0] = {
AIROHA_FUNC_MUX,
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
-@@ -30,20 +30,20 @@
+@@ -30,15 +30,15 @@
#include "../pinconf.h"
#include "../pinmux.h"
-#define PINCTRL_FUNC_DESC(id) \
+#define PINCTRL_FUNC_DESC(id, table) \
{ \
- .desc = { \
- .func = { \
- .name = #id, \
-- .groups = id##_groups, \
-- .ngroups = ARRAY_SIZE(id##_groups), \
-+ .groups = table##_groups, \
-+ .ngroups = ARRAY_SIZE(table##_groups), \
- } \
- }, \
+- .desc = PINCTRL_PINFUNCTION(#id, id##_groups, \
+- ARRAY_SIZE(id##_groups)), \
- .groups = id##_func_group, \
- .group_size = ARRAY_SIZE(id##_func_group), \
++ .desc = PINCTRL_PINFUNCTION(#id, table##_groups, \
++ ARRAY_SIZE(table##_groups)),\
+ .groups = table##_func_group, \
+ .group_size = ARRAY_SIZE(table##_func_group), \
}
#define PINCTRL_CONF_DESC(p, offset, mask) \
-@@ -362,16 +362,46 @@ struct airoha_pinctrl_gpiochip {
+@@ -357,16 +357,46 @@ struct airoha_pinctrl_gpiochip {
u32 irq_type[AIROHA_NUM_PINS];
};
PINCTRL_PIN(0, "uart1_txd"),
PINCTRL_PIN(1, "uart1_rxd"),
PINCTRL_PIN(2, "i2c_scl"),
-@@ -432,172 +462,172 @@ static struct pinctrl_pin_desc airoha_pi
+@@ -427,172 +457,172 @@ static struct pinctrl_pin_desc airoha_pi
PINCTRL_PIN(63, "pcie_reset2"),
};
};
static const char *const pon_groups[] = { "pon" };
-@@ -1960,33 +1990,33 @@ static const struct airoha_pinctrl_func_
+@@ -1955,33 +1985,33 @@ static const struct airoha_pinctrl_func_
},
};
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
-@@ -2047,7 +2077,7 @@ static const struct airoha_pinctrl_conf
+@@ -2042,7 +2072,7 @@ static const struct airoha_pinctrl_conf
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
};
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
-@@ -2108,7 +2138,7 @@ static const struct airoha_pinctrl_conf
+@@ -2103,7 +2133,7 @@ static const struct airoha_pinctrl_conf
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
};
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
-@@ -2169,7 +2199,7 @@ static const struct airoha_pinctrl_conf
+@@ -2164,7 +2194,7 @@ static const struct airoha_pinctrl_conf
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
};
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
-@@ -2230,7 +2260,7 @@ static const struct airoha_pinctrl_conf
+@@ -2225,7 +2255,7 @@ static const struct airoha_pinctrl_conf
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
};
PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
-@@ -2552,12 +2582,17 @@ airoha_pinctrl_get_conf_reg(const struct
+@@ -2547,12 +2577,17 @@ airoha_pinctrl_get_conf_reg(const struct
}
static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
if (!reg)
return -EINVAL;
-@@ -2570,12 +2605,17 @@ static int airoha_pinctrl_get_conf(struc
+@@ -2565,12 +2600,17 @@ static int airoha_pinctrl_get_conf(struc
}
static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
if (!reg)
return -EINVAL;
-@@ -2588,44 +2628,34 @@ static int airoha_pinctrl_set_conf(struc
+@@ -2583,44 +2623,34 @@ static int airoha_pinctrl_set_conf(struc
}
#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \
(pin), (val))
static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
-@@ -2804,12 +2834,13 @@ static int airoha_pinconf_set(struct pin
+@@ -2799,12 +2829,13 @@ static int airoha_pinconf_set(struct pin
static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev,
unsigned int group, unsigned long *config)
{
config))
return -ENOTSUPP;
-@@ -2826,13 +2857,14 @@ static int airoha_pinconf_group_set(stru
+@@ -2821,13 +2852,14 @@ static int airoha_pinconf_group_set(stru
unsigned int group, unsigned long *configs,
unsigned int num_configs)
{
configs, num_configs);
if (err)
return err;
-@@ -2858,23 +2890,16 @@ static const struct pinctrl_ops airoha_p
+@@ -2853,23 +2885,16 @@ static const struct pinctrl_ops airoha_p
.dt_free_map = pinconf_generic_dt_free_map,
};
pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
if (!pinctrl)
return -ENOMEM;
-@@ -2889,14 +2914,23 @@ static int airoha_pinctrl_probe(struct p
+@@ -2884,14 +2909,23 @@ static int airoha_pinctrl_probe(struct p
pinctrl->chip_scu = map;
err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name,
grp->pins, grp->npins,
-@@ -2909,10 +2943,10 @@ static int airoha_pinctrl_probe(struct p
+@@ -2904,10 +2938,10 @@ static int airoha_pinctrl_probe(struct p
}
/* build functions */
- func = &airoha_pinctrl_funcs[i];
+ func = &data->funcs[i];
err = pinmux_generic_add_function(pinctrl->ctrl,
- func->desc.func.name,
- func->desc.func.groups,
-@@ -2925,6 +2959,10 @@ static int airoha_pinctrl_probe(struct p
+ func->desc.name,
+ func->desc.groups,
+@@ -2920,6 +2954,10 @@ static int airoha_pinctrl_probe(struct p
}
}
err = pinctrl_enable(pinctrl->ctrl);
if (err)
return err;
-@@ -2933,8 +2971,39 @@ static int airoha_pinctrl_probe(struct p
+@@ -2928,8 +2966,39 @@ static int airoha_pinctrl_probe(struct p
return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
}
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
-@@ -1478,516 +1478,128 @@ static const struct airoha_pinctrl_func_
+@@ -1473,516 +1473,128 @@ static const struct airoha_pinctrl_func_
},
};
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
-@@ -1078,404 +1078,75 @@ static const struct airoha_pinctrl_func_
+@@ -1073,404 +1073,75 @@ static const struct airoha_pinctrl_func_
};
/* PWM */
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
-@@ -75,6 +75,7 @@
+@@ -70,6 +70,7 @@
#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
#define GPIO_PCM_SPI_MODE_MASK BIT(16)
#define GPIO_PCM2_MODE_MASK BIT(13)
-@@ -132,6 +133,8 @@
+@@ -127,6 +128,8 @@
/* CONF */
#define REG_I2C_SDA_E2 0x001c
#define SPI_MISO_E2_MASK BIT(14)
#define SPI_MOSI_E2_MASK BIT(13)
#define SPI_CLK_E2_MASK BIT(12)
-@@ -139,12 +142,16 @@
+@@ -134,12 +137,16 @@
#define PCIE2_RESET_E2_MASK BIT(10)
#define PCIE1_RESET_E2_MASK BIT(9)
#define PCIE0_RESET_E2_MASK BIT(8)
#define SPI_MISO_E4_MASK BIT(14)
#define SPI_MOSI_E4_MASK BIT(13)
#define SPI_CLK_E4_MASK BIT(12)
-@@ -152,6 +159,8 @@
+@@ -147,6 +154,8 @@
#define PCIE2_RESET_E4_MASK BIT(10)
#define PCIE1_RESET_E4_MASK BIT(9)
#define PCIE0_RESET_E4_MASK BIT(8)
#define UART1_RXD_E4_MASK BIT(3)
#define UART1_TXD_E4_MASK BIT(2)
#define I2C_SCL_E4_MASK BIT(1)
-@@ -163,6 +172,8 @@
+@@ -158,6 +167,8 @@
#define REG_GPIO_H_E4 0x0030
#define REG_I2C_SDA_PU 0x0044
#define SPI_MISO_PU_MASK BIT(14)
#define SPI_MOSI_PU_MASK BIT(13)
#define SPI_CLK_PU_MASK BIT(12)
-@@ -170,12 +181,16 @@
+@@ -165,12 +176,16 @@
#define PCIE2_RESET_PU_MASK BIT(10)
#define PCIE1_RESET_PU_MASK BIT(9)
#define PCIE0_RESET_PU_MASK BIT(8)
#define SPI_MISO_PD_MASK BIT(14)
#define SPI_MOSI_PD_MASK BIT(13)
#define SPI_CLK_PD_MASK BIT(12)
-@@ -183,6 +198,8 @@
+@@ -178,6 +193,8 @@
#define PCIE2_RESET_PD_MASK BIT(10)
#define PCIE1_RESET_PD_MASK BIT(9)
#define PCIE0_RESET_PD_MASK BIT(8)
#define UART1_RXD_PD_MASK BIT(3)
#define UART1_TXD_PD_MASK BIT(2)
#define I2C_SCL_PD_MASK BIT(1)
-@@ -630,10 +647,223 @@ static const struct pingroup en7581_pinc
+@@ -625,10 +642,223 @@ static const struct pingroup en7581_pinc
PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
};
static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
"hsuart_cts_rts", "uart4",
"uart5" };
-@@ -646,11 +876,16 @@ static const char *const pcm_spi_groups[
+@@ -641,11 +871,16 @@ static const char *const pcm_spi_groups[
"pcm_spi_cs2_p156",
"pcm_spi_cs2_p128",
"pcm_spi_cs3", "pcm_spi_cs4" };
static const char *const pwm_groups[] = { "gpio0", "gpio1",
"gpio2", "gpio3",
"gpio4", "gpio5",
-@@ -689,6 +924,22 @@ static const char *const phy3_led1_group
+@@ -684,6 +919,22 @@ static const char *const phy3_led1_group
"gpio45", "gpio46" };
static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
"gpio45", "gpio46" };
static const struct airoha_pinctrl_func_group pon_func_group[] = {
{
-@@ -766,6 +1017,25 @@ static const struct airoha_pinctrl_func_
+@@ -761,6 +1012,25 @@ static const struct airoha_pinctrl_func_
},
};
static const struct airoha_pinctrl_func_group uart_func_group[] = {
{
.name = "uart2",
-@@ -1007,6 +1277,73 @@ static const struct airoha_pinctrl_func_
+@@ -1002,6 +1272,73 @@ static const struct airoha_pinctrl_func_
},
};
static const struct airoha_pinctrl_func_group i2s_func_group[] = {
{
.name = "i2s",
-@@ -1077,6 +1414,28 @@ static const struct airoha_pinctrl_func_
+@@ -1072,6 +1409,28 @@ static const struct airoha_pinctrl_func_
},
};
/* PWM */
#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
{ \
-@@ -1273,6 +1632,94 @@ static const struct airoha_pinctrl_func_
+@@ -1268,6 +1627,94 @@ static const struct airoha_pinctrl_func_
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("pon", pon),
PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
-@@ -1299,6 +1746,31 @@ static const struct airoha_pinctrl_func
+@@ -1294,6 +1741,31 @@ static const struct airoha_pinctrl_func
PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
};
static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
-@@ -1360,6 +1832,62 @@ static const struct airoha_pinctrl_conf
+@@ -1355,6 +1827,62 @@ static const struct airoha_pinctrl_conf
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
};
static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
-@@ -1421,6 +1949,62 @@ static const struct airoha_pinctrl_conf
+@@ -1416,6 +1944,62 @@ static const struct airoha_pinctrl_conf
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
};
static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
-@@ -1482,6 +2066,62 @@ static const struct airoha_pinctrl_conf
+@@ -1477,6 +2061,62 @@ static const struct airoha_pinctrl_conf
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
};
static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
-@@ -1543,12 +2183,73 @@ static const struct airoha_pinctrl_conf
+@@ -1538,12 +2178,73 @@ static const struct airoha_pinctrl_conf
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
};
static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
struct pinctrl_gpio_range *range,
int pin)
-@@ -1714,7 +2415,7 @@ static const struct irq_chip airoha_gpio
+@@ -1709,7 +2410,7 @@ static const struct irq_chip airoha_gpio
};
static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
{
struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
struct gpio_chip *gc = &chip->chip;
-@@ -1749,7 +2450,7 @@ static int airoha_pinctrl_add_gpiochip(s
+@@ -1744,7 +2445,7 @@ static int airoha_pinctrl_add_gpiochip(s
return irq;
err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED,
if (err) {
dev_err(dev, "error requesting irq %d: %d\n", irq, err);
return err;
-@@ -1813,8 +2514,8 @@ static int airoha_pinmux_set_mux(struct
+@@ -1808,8 +2509,8 @@ static int airoha_pinmux_set_mux(struct
}
static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev,
{
struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
u32 mask, index;
-@@ -1904,7 +2605,7 @@ static int airoha_pinctrl_set_conf(struc
+@@ -1899,7 +2600,7 @@ static int airoha_pinctrl_set_conf(struc
if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask,
return -EINVAL;
return 0;
-@@ -2123,8 +2824,8 @@ static int airoha_pinconf_group_get(stru
+@@ -2118,8 +2819,8 @@ static int airoha_pinconf_group_get(stru
for (i = 0; i < pinctrl->grps[group].npins; i++) {
if (airoha_pinconf_get(pctrl_dev,
return -ENOTSUPP;
if (i && cur_config != *config)
-@@ -2285,8 +2986,40 @@ static const struct airoha_pinctrl_match
+@@ -2280,8 +2981,40 @@ static const struct airoha_pinctrl_match
},
};
--- /dev/null
+From f2bd5a0f59d052d16749bccf637690e51947a5d6 Mon Sep 17 00:00:00 2001
+Date: Sat, 15 Nov 2025 18:00:00 +0800
+Subject: [PATCH] pinctrl: airoha: fix pinctrl function mismatch issue
+
+The blamed commit made the following changes:
+
+-#define PINCTRL_FUNC_DESC(id)...
+- .desc = PINCTRL_PINFUNCTION(#id, ...
++#define PINCTRL_FUNC_DESC(id, table)...
++ .desc = PINCTRL_PINFUNCTION(#id, ...
+
+- PINCTRL_FUNC_DESC(pon)...
++ PINCTRL_FUNC_DESC("pon", pon)...
+
+It's clear that the id of funcs doesn't match the definition.
+Remove redundant #string from the definition to fix this issue:
+pinctrl-airoha ...: invalid function mdio in map table
+
+Fixes: 4043b0c45f85 ("pinctrl: airoha: generalize pins/group/function/confs handling")
+---
+ drivers/pinctrl/mediatek/pinctrl-airoha.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
++++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+@@ -35,7 +35,7 @@
+
+ #define PINCTRL_FUNC_DESC(id, table) \
+ { \
+- .desc = PINCTRL_PINFUNCTION(#id, table##_groups, \
++ .desc = PINCTRL_PINFUNCTION(id, table##_groups, \
+ ARRAY_SIZE(table##_groups)),\
+ .groups = table##_func_group, \
+ .group_size = ARRAY_SIZE(table##_func_group), \
--- /dev/null
+From 0341d1b1ebf10bcbb9f35e174e83dbb21068387d Mon Sep 17 00:00:00 2001
+Date: Wed, 12 Nov 2025 11:44:30 -0700
+Subject: [PATCH] pinctrl: airoha: Fix AIROHA_PINCTRL_CONFS_DRIVE_E2 in
+ an7583_pinctrl_match_data
+
+Clang warns (or errors with CONFIG_WERROR=y / W=e):
+
+ pinctrl/mediatek/pinctrl-airoha.c:2064:41: error: variable 'an7583_pinctrl_drive_e2_conf' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration]
+ 2064 | static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
+ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Due to a typo, an7583_pinctrl_drive_e2_conf is only used within
+ARRAY_SIZE() (hence no instance of -Wunused-variable), which is
+evaluated at compile time, so it will not be needed in the final object
+file.
+
+Fix the .confs assignment for AIROHA_PINCTRL_CONFS_DRIVE_E2 in
+an7583_pinctrl_match_data to clear up the warning.
+
+Closes: https://github.com/ClangBuiltLinux/linux/issues/2142
+Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
+---
+ drivers/pinctrl/mediatek/pinctrl-airoha.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
++++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+@@ -2998,7 +2998,7 @@ static const struct airoha_pinctrl_match
+ .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+- .confs = en7581_pinctrl_drive_e2_conf,
++ .confs = an7583_pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {