clk: si5351: Fix clkout rate computation.

Rate was incorrectly computed because we read from wrong divider register.

Signed-off-by: Marek Belisko <[email protected]>
Acked-by: Sebastian Hesselbarth <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>
Cc: [email protected]

diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 892728412e9ddb0af46ec0a7f93cdeceadc4ed40..cf39e530e6e2a26687ee61fcfca261db1ff83cd9 100644 (file)
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
        unsigned char reg;
        unsigned char rdiv;
 
-       if (hwdata->num > 5)
+       if (hwdata->num <= 5)
                reg = si5351_msynth_params_address(hwdata->num) + 2;
        else
                reg = SI5351_CLK6_7_OUTPUT_DIVIDER;