ti: k3: common: Use coherent memory for shared data

HW_ASSISTED_COHERENCY implies something stronger than just hardware
coherent interconnect, specifically a DynamIQ capable ARM core.

For K3, lets use WARMBOOT_ENABLE_DCACHE_EARLY to enable caches early
and then let the caches get shut off on powerdown, to prevent data
corruption we also need to USE_COHERENT_MEM so that any accesses to
shared memory after this point is only to memory that is set as
non-cached for all cores.

Change-Id: Ib9337f012df0e0388237942607c501b6f3e2a949
Signed-off-by: Andrew F. Davis <[email protected]>

diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index 2e5f5845365c35da470b59df99462ecb11165714..3613a0e2f028f22f6839ebfd82c49ac3403441bf 100644 (file)
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -12,8 +12,8 @@ COLD_BOOT_SINGLE_CPU  :=      1
 PROGRAMMABLE_RESET_ADDRESS:=   1
 
 # System coherency is managed in hardware
-HW_ASSISTED_COHERENCY  :=      1
-USE_COHERENT_MEM       :=      0
+WARMBOOT_ENABLE_DCACHE_EARLY :=        1
+USE_COHERENT_MEM       :=      1
 
 # A53 erratum for SoC. (enable them all)
 ERRATA_A53_826319      :=      1