ath79: increase spi clock for D-Link DIR-842

AHB is 258 MHz for this device (CPU_PLL / 3), but there is no difference
between 64 MHz and 50 MHz for spi-max-frequency, thus increase to 50 MHz.

Tested on revisions C1 and C3.

Signed-off-by: Sebastian Schaper <[email protected]>

diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi b/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi
index 8071332451e9c1221ecefe6cd2f0a77e2ce88581..6b2fb1c4a0c9fdf6e1b2b9b3fa824a4f690d5b58 100644 (file)
--- a/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi
+++ b/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi
@@ -37,12 +37,13 @@
 
 &spi {
        status = "okay";
+
        num-cs = <1>;
 
        flash@0 {
                compatible = "jedec,spi-nor";
                reg = <0>;
-               spi-max-frequency = <30000000>;
+               spi-max-frequency = <50000000>;
 
                partitions {
                        compatible = "fixed-partitions";