armv7: hw_data: change clock divider setting.

Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,

f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)

fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.

Signed-off-by: Sourav Poddar <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index c00bfb8d30cb6f5e16d85eb14ad190ef847240bd..a1b249e734376253536d24a1bf317010ff952b99 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -170,7 +170,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
        {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 12 MHz   */
-       {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 20 MHz   */
+       {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 20 MHz   */
        {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 16.8 MHz */
        {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 19.2 MHz */
        {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},           /* 26 MHz   */