rpi3: Fix warm entrypoint setup for PSCI_CPU_ON
authorAntonio Nino Diaz <[email protected]>
Sat, 14 Jul 2018 00:22:43 +0000 (01:22 +0100)
committerAntonio Nino Diaz <[email protected]>
Mon, 16 Jul 2018 14:56:42 +0000 (15:56 +0100)
Remove unused variable and set the secure entrypoint correctly.

Change-Id: I7447ea62771092de6be35704077ae28c519d6993
Signed-off-by: Antonio Nino Diaz <[email protected]>
plat/rpi3/include/platform_def.h
plat/rpi3/rpi3_pm.c

index 5b84aa617416178f9a28e302eb023bcd10b1cddd..52b06b4b84c9fa6d770f5bfb0a1733007f4b8f08 100644 (file)
  */
 #define PLAT_RPI3_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE
 
+/* The secure entry point to be used on warm reset by all CPUs. */
 #define PLAT_RPI3_TM_ENTRYPOINT                PLAT_RPI3_TRUSTED_MAILBOX_BASE
 #define PLAT_RPI3_TM_ENTRYPOINT_SIZE   ULL(8)
 
+/* Hold entries for each CPU. */
 #define PLAT_RPI3_TM_HOLD_BASE         (PLAT_RPI3_TM_ENTRYPOINT + \
                                         PLAT_RPI3_TM_ENTRYPOINT_SIZE)
 #define PLAT_RPI3_TM_HOLD_ENTRY_SIZE   ULL(8)
index 96948580ec5dc09a3ef2a448b7b55d0da7862dcf..b6adc8a5305f27eceb469772ff22be70e9c35b9b 100644 (file)
 
 #include "rpi3_hw.h"
 
-/*
- * The secure entry point to be used on warm reset.
- */
-static uintptr_t secure_entrypoint;
-
 /* Make composite power state parameter till power level 0 */
 #if PSCI_EXTENDED_STATE_ID
 
@@ -220,10 +215,9 @@ static const plat_psci_ops_t plat_rpi3_psci_pm_ops = {
 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
                        const plat_psci_ops_t **psci_ops)
 {
-       uintptr_t *mailbox = (void *)PLAT_RPI3_TRUSTED_MAILBOX_BASE;
+       uintptr_t *entrypoint = (void *) PLAT_RPI3_TM_ENTRYPOINT;
 
-       *mailbox = sec_entrypoint;
-       secure_entrypoint = (uintptr_t)sec_entrypoint;
+       *entrypoint = sec_entrypoint;
        *psci_ops = &plat_rpi3_psci_pm_ops;
 
        return 0;