drm/i915: update watermarks before enabling PLLs

When coming back from DPMS or turning on a display, make sure we have
the watermarks set up before turning on the display plane, otherwise we
may get underruns.

Signed-off-by: Jesse Barnes <[email protected]>
Tested-by: Dirk Hohndel <[email protected]>
Signed-off-by: Eric Anholt <[email protected]>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 47d6ff058991b5c632fe73d225879d3200bcdd54..7eed3db5451d5f363a527ad7c55aed2f951bb18e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1803,6 +1803,8 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
        case DRM_MODE_DPMS_ON:
        case DRM_MODE_DPMS_STANDBY:
        case DRM_MODE_DPMS_SUSPEND:
+               intel_update_watermarks(dev);
+
                /* Enable the DPLL */
                temp = I915_READ(dpll_reg);
                if ((temp & DPLL_VCO_ENABLE) == 0) {
@@ -1840,7 +1842,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
 
                /* Give the overlay scaler a chance to enable if it's on this pipe */
                //intel_crtc_dpms_video(crtc, true); TODO
-               intel_update_watermarks(dev);
        break;
        case DRM_MODE_DPMS_OFF:
                intel_update_watermarks(dev);