--- /dev/null
+From 3ca743f8a5b568dc5e5d5f1bab0298a4a43c2360 Mon Sep 17 00:00:00 2001
+Date: Fri, 27 Sep 2024 14:42:22 +0200
+Subject: arm64: dts: rockchip: Switch to hp-det-gpios
+
+Replace the deprecated "hp-det-gpio" property by "hp-det-gpios" in Audio
+Graph Card and Realtek RT5651 Audio Codec device nodes.
+
+Link: https://lore.kernel.org/r/717e7c9527139c3a3e5246dd367a3ad98c5c81b6.1727438777.git.geert+renesas@glider.be
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+@@ -46,7 +46,7 @@
+ compatible = "audio-graph-card";
+ label = "rk3588-es8316";
+ dais = <&i2s0_8ch_p0>;
+- hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
++ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ routing = "MIC2", "Mic Jack",
--- /dev/null
+From e684f02492f99d6f6f037a35a613607339cf8e8f Mon Sep 17 00:00:00 2001
+Date: Fri, 6 Sep 2024 10:25:11 +0200
+Subject: arm64: dts: rockchip: fix the pcie refclock oscillator on Rock 5 ITX
+
+The Rock 5 ITX uses two PCIe controllers to drive both a M.2 slot and its
+SATA controller with 2 lanes each. The supply for the refclk oscillator is
+the same that supplies the M.2 slot, but the SATA controller port is
+supplied by a different rail.
+
+This leads to the effect that if the PCIe30x4 controller for the M.2
+probes first, everything works normally. But if the PCIe30x2 controller
+that is connected to the SATA controller probes first, it will hang on
+the first DBI read as nothing will have enabled the refclock before.
+
+Fix this by describing the clock generator with its supplies so that
+both controllers can reference it as needed.
+
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+@@ -72,6 +72,15 @@
+ };
+ };
+
++ /* Unnamed gated oscillator: 100MHz,3.3V,3225 */
++ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
++ compatible = "gated-fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <100000000>;
++ clock-output-names = "pcie30_refclk";
++ vdd-supply = <&vcc3v3_pi6c_05>;
++ };
++
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+@@ -146,13 +155,14 @@
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+- vcc3v3_mkey: regulator-vcc3v3-mkey {
++ /* The PCIE30x4_PWREN_H controls two regulators */
++ vcc3v3_mkey: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x4_pwren_h>;
+- regulator-name = "vcc3v3_mkey";
++ regulator-name = "vcc3v3_pi6c_05";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+@@ -513,6 +523,18 @@
+
+ /* ASMedia ASM1164 Sata controller */
+ &pcie3x2 {
++ /*
++ * The board has a "pcie_refclk" oscillator that needs enabling,
++ * so add it to the list of clocks.
++ */
++ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
++ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
++ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>,
++ <&pcie30_port1_refclk>;
++ clock-names = "aclk_mst", "aclk_slv",
++ "aclk_dbi", "pclk",
++ "aux", "pipe",
++ "ref";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x2_perstn_m1_l>;
+ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+@@ -522,6 +544,18 @@
+
+ /* M.2 M.key */
+ &pcie3x4 {
++ /*
++ * The board has a "pcie_refclk" oscillator that needs enabling,
++ * so add it to the list of clocks.
++ */
++ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
++ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
++ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
++ <&pcie30_port0_refclk>;
++ clock-names = "aclk_mst", "aclk_slv",
++ "aclk_dbi", "pclk",
++ "aux", "pipe",
++ "ref";
+ num-lanes = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x4_perstn_m1_l>;
--- /dev/null
+From b36402e4a0772d1b3da06a4f5fbd1cfe4d6f1cc0 Mon Sep 17 00:00:00 2001
+Date: Fri, 28 Feb 2025 22:33:08 +0800
+Subject: arm64: dts: rockchip: slow down emmc freq for rock 5 itx
+
+The current max-frequency 200000000 of emmc is not stable. When doing
+heavy write there will be I/O Error. After setting max-frequency to
+150000000 the emmc is stable under write.
+
+Also remove property mmc-hs200-1_8v because we are already running at
+HS400 mode.
+
+Tested with fio command:
+fio -filename=./test_randread -direct=1 -iodepth 1 -thread \
+-rw=randwrite -ioengine=psync -bs=16k -size=1G -numjobs=10 \
+-runtime=600 -group_reporting -name=mytest
+
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+@@ -690,10 +690,9 @@
+
+ &sdhci {
+ bus-width = <8>;
+- max-frequency = <200000000>;
++ max-frequency = <150000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+- mmc-hs200-1_8v;
+ no-sdio;
+ no-sd;
+ non-removable;
--- /dev/null
+From 3eac9319af62dbc56d1f06fcb240e4a092fa5b2f Mon Sep 17 00:00:00 2001
+Date: Tue, 25 Feb 2025 11:08:48 +0800
+Subject: arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITX
+
+Enable the HDMI port next to ethernet port.
+
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+@@ -11,6 +11,7 @@
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/pwm/pwm.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "dt-bindings/usb/pd.h"
+ #include "rk3588.dtsi"
+
+@@ -72,6 +73,17 @@
+ };
+ };
+
++ hdmi1-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi1_con_in: endpoint {
++ remote-endpoint = <&hdmi1_out_con>;
++ };
++ };
++ };
++
+ /* Unnamed gated oscillator: 100MHz,3.3V,3225 */
+ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
+ compatible = "gated-fixed-clock";
+@@ -261,6 +273,28 @@
+ status = "okay";
+ };
+
++&hdmi1 {
++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
++ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
++ status = "okay";
++};
++
++&hdmi1_in {
++ hdmi1_in_vp1: endpoint {
++ remote-endpoint = <&vp1_out_hdmi1>;
++ };
++};
++
++&hdmi1_out {
++ hdmi1_out_con: endpoint {
++ remote-endpoint = <&hdmi1_con_in>;
++ };
++};
++
++&hdptxphy1 {
++ status = "okay";
++};
++
+ &i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+@@ -1208,3 +1242,18 @@
+ rockchip,dp-lane-mux = <2 3>;
+ status = "okay";
+ };
++
++&vop {
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp1 {
++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI1>;
++ remote-endpoint = <&hdmi1_in_vp1>;
++ };
++};
--- /dev/null
+From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001
+Date: Thu, 20 Feb 2025 19:58:11 +0100
+Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for
+ RK3588
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Enabling the GPU power domain requires that the GPU regulator is
+enabled. The regulator is enabled at boot time, but gets disabled
+automatically when there are no users.
+
+This means the system might run into a failure state hanging the
+whole system for the following use cases:
+
+ * if the GPU driver is being probed late (e.g. build as a
+ module and firmware is not in initramfs), the regulator
+ might already have been disabled. In that case the power
+ domain is enabled before the regulator.
+ * unbinding the GPU driver will disable the PM domain and
+ the regulator. When the driver is bound again, the PM
+ domain will be enabled before the regulator and error
+ appears.
+
+Avoid this by adding an explicit regulator dependency to the
+power domain.
+
+Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+@@ -598,6 +598,10 @@
+ status = "okay";
+ };
+
++&pd_gpu {
++ domain-supply = <&vdd_gpu_s0>;
++};
++
+ &pinctrl {
+ hym8563 {
+ rtc_int: rtc-int {
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+@@ -23,6 +23,10 @@
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
++ led-boot = &power_led;
++ led-failsafe = &power_led;
++ led-running = &power_led;
++ led-upgrade = &power_led;
+ };
+
+ chosen {
+@@ -62,12 +66,14 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+- power-led1 {
++ power_led: power-led1 {
++ default-state = "on";
++ function = LED_FUNCTION_POWER;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "default-on";
+ };
+
+ hdd-led2 {
++ function = LED_FUNCTION_DISK;
+ gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ };
projects / openwrt / staging / nbd.git / commitdiff