rcar_gen3: drivers: qos: H3: Use common register definition

Use common qos_regs.h instead of a local copy in the H3 QoS init.
Fill missing registers into qos_regs.h . No functional change.

Signed-off-by: Marek Vasut <[email protected]>
Change-Id: I0b5ceab71be07e270885bdff403e5292e3373787

diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
index 21aa3df039f02b19ecea56f9dc09260e85b67372..29ef0b6db2b4d5ee6f9e14162f4016a252ac71aa 100644 (file)
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,50 +9,11 @@
 #include <common/debug.h>
 
 #include "../qos_common.h"
+#include "../qos_reg.h"
 #include "qos_init_h3_v10.h"
 
 #define        RCAR_QOS_VERSION                "rev.0.36"
 
-#define        RCAR_QOS_NONE                   (3U)
-#define        RCAR_QOS_TYPE_DEFAULT           (0U)
-
-#define        RCAR_DRAM_SPLIT_LINEAR          (0U)
-#define        RCAR_DRAM_SPLIT_4CH             (1U)
-#define        RCAR_DRAM_SPLIT_2CH             (2U)
-#define        RCAR_DRAM_SPLIT_AUTO            (3U)
-
-#define        AXI_BASE                        (0xE6784000U)
-#define        AXI_ADSPLCR0                    (AXI_BASE + 0x0008U)
-#define        AXI_ADSPLCR1                    (AXI_BASE + 0x000CU)
-#define        AXI_ADSPLCR2                    (AXI_BASE + 0x0010U)
-#define        AXI_ADSPLCR3                    (AXI_BASE + 0x0014U)
-#define        ADSPLCR0_ADRMODE_DEFAULT        ((uint32_t)0U << 31U)
-#define        ADSPLCR0_ADRMODE_GEN2           ((uint32_t)1U << 31U)
-#define        ADSPLCR0_SPLITSEL(x)            ((uint32_t)(x) << 16U)
-#define        ADSPLCR0_AREA(x)                ((uint32_t)(x) <<  8U)
-#define        ADSPLCR0_SWP                    (0x0CU)
-
-#define        MSTAT_BASE                      (0xE67E0000U)
-#define        MSTAT_FIX_QOS_BANK0             (MSTAT_BASE + 0x0000U)
-#define        MSTAT_FIX_QOS_BANK1             (MSTAT_BASE + 0x1000U)
-#define        MSTAT_BE_QOS_BANK0              (MSTAT_BASE + 0x2000U)
-#define        MSTAT_BE_QOS_BANK1              (MSTAT_BASE + 0x3000U)
-#define        MSTAT_SL_INIT                   (MSTAT_BASE + 0x8000U)
-#define        MSTAT_REF_ARS                   (MSTAT_BASE + 0x8004U)
-#define        MSTAT_STATQC                    (MSTAT_BASE + 0x8008U)
-
-#define        RALLOC_BASE                     (0xE67F0000U)
-#define        RALLOC_RAS                      (RALLOC_BASE + 0x0000U)
-#define        RALLOC_FIXTH                    (RALLOC_BASE + 0x0004U)
-#define        RALLOC_RAEN                     (RALLOC_BASE + 0x0018U)
-#define        RALLOC_REGGD                    (RALLOC_BASE + 0x0020U)
-#define        RALLOC_DANN                     (RALLOC_BASE + 0x0030U)
-#define        RALLOC_DANT                     (RALLOC_BASE + 0x0038U)
-#define        RALLOC_EC                       (RALLOC_BASE + 0x003CU)
-#define        RALLOC_EMS                      (RALLOC_BASE + 0x0040U)
-#define        RALLOC_INSFC                    (RALLOC_BASE + 0x0050U)
-#define        RALLOC_BERR                     (RALLOC_BASE + 0x0054U)
-
 #if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
 static const mstat_slot_t mstat_fix[] = {
        {0x0000U, 0x0000000000000000UL},
@@ -305,32 +266,32 @@ void qos_init_h3_v10(void)
        io_write_32(0xE67D1008U, 0x00000100U);
 
        /* Resource Alloc setting */
-       io_write_32(RALLOC_RAS, 0x00000040U);
-       io_write_32(RALLOC_FIXTH, 0x000F0005U);
-       io_write_32(RALLOC_REGGD, 0x00000004U);
-       io_write_64(RALLOC_DANN, 0x0202000004040404UL);
-       io_write_32(RALLOC_DANT, 0x003C1110U);
-       io_write_32(RALLOC_EC, 0x00080001U);    /* need for H3 v1.* */
-       io_write_64(RALLOC_EMS, 0x0000000000000000UL);
-       io_write_32(RALLOC_INSFC, 0xC7840001U);
-       io_write_32(RALLOC_BERR, 0x00000000U);
+       io_write_32(QOSCTRL_RAS, 0x00000040U);
+       io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
+       io_write_32(QOSCTRL_REGGD, 0x00000004U);
+       io_write_64(QOSCTRL_DANN, 0x0202000004040404UL);
+       io_write_32(QOSCTRL_DANT, 0x003C1110U);
+       io_write_32(QOSCTRL_EC, 0x00080001U);   /* need for H3 v1.* */
+       io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
+       io_write_32(QOSCTRL_INSFC, 0xC7840001U);
+       io_write_32(QOSCTRL_BERR, 0x00000000U);
 
-       /* MSTAT setting */
-       io_write_32(MSTAT_SL_INIT,
+       /* QOSBW setting */
+       io_write_32(QOSCTRL_SL_INIT,
                    SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
-       io_write_32(MSTAT_REF_ARS, 0x00330000U);
+       io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
 
-       /* MSTAT SRAM setting */
+       /* QOSBW SRAM setting */
        for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
-               io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
+               io_write_64(QOSBW_FIX_QOS_BANK0 + mstat_fix[i].addr,
                        mstat_fix[i].value);
-               io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
+               io_write_64(QOSBW_FIX_QOS_BANK1 + mstat_fix[i].addr,
                        mstat_fix[i].value);
        }
        for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
-               io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
+               io_write_64(QOSBW_BE_QOS_BANK0 + mstat_be[i].addr,
                        mstat_be[i].value);
-               io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
+               io_write_64(QOSBW_BE_QOS_BANK1 + mstat_be[i].addr,
                        mstat_be[i].value);
        }
 
@@ -346,14 +307,14 @@ void qos_init_h3_v10(void)
        io_write_32(0xFD827800U, 0x0000003FU);
 
        /* Resource Alloc start */
-       io_write_32(RALLOC_RAEN, 0x00000001U);
+       io_write_32(QOSCTRL_RAEN, 0x00000001U);
 
-       /* MSTAT start */
-       io_write_32(MSTAT_STATQC, 0x00000001U);
+       /* QOSBW start */
+       io_write_32(QOSCTRL_STATQC, 0x00000001U);
 #else
        NOTICE("BL2: QoS is None\n");
 
        /* Resource Alloc setting */
-       io_write_32(RALLOC_EC, 0x00080001U);    /* need for H3 v1.* */
+       io_write_32(QOSCTRL_EC, 0x00080001U);   /* need for H3 v1.* */
 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
 }

diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
index 5b7348ce0ae8230af1ce6596f5161602cc43b41a..e9491dc414d65a7465bc1290ddb4336fdec8a02b 100644 (file)
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,137 +11,11 @@
 #include <rcar_def.h>
 
 #include "../qos_common.h"
+#include "../qos_reg.h"
 #include "qos_init_h3_v11.h"
 
 #define        RCAR_QOS_VERSION                "rev.0.37"
 
-#define        RCAR_QOS_NONE                   (3U)
-#define        RCAR_QOS_TYPE_DEFAULT           (0U)
-
-#define        RCAR_DRAM_SPLIT_LINEAR          (0U)
-#define        RCAR_DRAM_SPLIT_4CH             (1U)
-#define        RCAR_DRAM_SPLIT_2CH             (2U)
-#define        RCAR_DRAM_SPLIT_AUTO            (3U)
-
-#define        RST_BASE                        (0xE6160000U)
-#define        RST_MODEMR                      (RST_BASE + 0x0060U)
-
-#define        RCAR_PWRSR8                     (0xE6180340U)   /* A3VP_PWRSR0 */
-#define        RCAR_PWRONCR8                   (0xE618034CU)   /* A3VP_PWRONCR */
-#define        RCAR_PWRSR9                     (0xE6180380U)   /* A3VC_PWRSR0 */
-#define        RCAR_PWRONCR9                   (0xE618038CU)   /* A3VC_PWRONCR */
-#define        RCAR_PWRSR10                    (0xE61803C0U)   /* A2VC_PWRSR0 */
-#define        RCAR_PWRONCR10                  (0xE61803CCU)   /* A2VC_PWRONCR */
-
-#define        DBSC_BASE                       (0xE6790000U)
-#define DBSC_DBCAM0CNF0                        (DBSC_BASE + 0x0900U)
-#define DBSC_DBCAM0CNF1                        (DBSC_BASE + 0x0904U)
-#define DBSC_DBCAM0CNF2                        (DBSC_BASE + 0x0908U)
-#define DBSC_DBCAM0CNF3                        (DBSC_BASE + 0x090CU)
-#define DBSC_DBCAMDIS                  (DBSC_BASE + 0x09fCU)
-#define DBSC_DBSCHCNT0                 (DBSC_BASE + 0x1000U)
-#define DBSC_DBSCHCNT1                 (DBSC_BASE + 0x1004U)
-#define DBSC_DBSCHSZ0                  (DBSC_BASE + 0x1010U)
-#define DBSC_DBSCHRW0                  (DBSC_BASE + 0x1020U)
-#define DBSC_DBSCHQOS_0_0              (DBSC_BASE + 0x1030U)
-#define DBSC_DBSCHQOS_0_1              (DBSC_BASE + 0x1034U)
-#define DBSC_DBSCHQOS_0_2              (DBSC_BASE + 0x1038U)
-#define DBSC_DBSCHQOS_0_3              (DBSC_BASE + 0x103CU)
-#define DBSC_DBSCHQOS_1_0              (DBSC_BASE + 0x1040U)
-#define DBSC_DBSCHQOS_1_1              (DBSC_BASE + 0x1044U)
-#define DBSC_DBSCHQOS_1_2              (DBSC_BASE + 0x1048U)
-#define DBSC_DBSCHQOS_1_3              (DBSC_BASE + 0x104CU)
-#define DBSC_DBSCHQOS_2_0              (DBSC_BASE + 0x1050U)
-#define DBSC_DBSCHQOS_2_1              (DBSC_BASE + 0x1054U)
-#define DBSC_DBSCHQOS_2_2              (DBSC_BASE + 0x1058U)
-#define DBSC_DBSCHQOS_2_3              (DBSC_BASE + 0x105CU)
-#define DBSC_DBSCHQOS_3_0              (DBSC_BASE + 0x1060U)
-#define DBSC_DBSCHQOS_3_1              (DBSC_BASE + 0x1064U)
-#define DBSC_DBSCHQOS_3_2              (DBSC_BASE + 0x1068U)
-#define DBSC_DBSCHQOS_3_3              (DBSC_BASE + 0x106CU)
-#define DBSC_DBSCHQOS_4_0              (DBSC_BASE + 0x1070U)
-#define DBSC_DBSCHQOS_4_1              (DBSC_BASE + 0x1074U)
-#define DBSC_DBSCHQOS_4_2              (DBSC_BASE + 0x1078U)
-#define DBSC_DBSCHQOS_4_3              (DBSC_BASE + 0x107CU)
-#define DBSC_DBSCHQOS_5_0              (DBSC_BASE + 0x1080U)
-#define DBSC_DBSCHQOS_5_1              (DBSC_BASE + 0x1084U)
-#define DBSC_DBSCHQOS_5_2              (DBSC_BASE + 0x1088U)
-#define DBSC_DBSCHQOS_5_3              (DBSC_BASE + 0x108CU)
-#define DBSC_DBSCHQOS_6_0              (DBSC_BASE + 0x1090U)
-#define DBSC_DBSCHQOS_6_1              (DBSC_BASE + 0x1094U)
-#define DBSC_DBSCHQOS_6_2              (DBSC_BASE + 0x1098U)
-#define DBSC_DBSCHQOS_6_3              (DBSC_BASE + 0x109CU)
-#define DBSC_DBSCHQOS_7_0              (DBSC_BASE + 0x10A0U)
-#define DBSC_DBSCHQOS_7_1              (DBSC_BASE + 0x10A4U)
-#define DBSC_DBSCHQOS_7_2              (DBSC_BASE + 0x10A8U)
-#define DBSC_DBSCHQOS_7_3              (DBSC_BASE + 0x10ACU)
-#define DBSC_DBSCHQOS_8_0              (DBSC_BASE + 0x10B0U)
-#define DBSC_DBSCHQOS_8_1              (DBSC_BASE + 0x10B4U)
-#define DBSC_DBSCHQOS_8_2              (DBSC_BASE + 0x10B8U)
-#define DBSC_DBSCHQOS_8_3              (DBSC_BASE + 0x10BCU)
-#define DBSC_DBSCHQOS_9_0              (DBSC_BASE + 0x10C0U)
-#define DBSC_DBSCHQOS_9_1              (DBSC_BASE + 0x10C4U)
-#define DBSC_DBSCHQOS_9_2              (DBSC_BASE + 0x10C8U)
-#define DBSC_DBSCHQOS_9_3              (DBSC_BASE + 0x10CCU)
-#define DBSC_DBSCHQOS_10_0             (DBSC_BASE + 0x10D0U)
-#define DBSC_DBSCHQOS_10_1             (DBSC_BASE + 0x10D4U)
-#define DBSC_DBSCHQOS_10_2             (DBSC_BASE + 0x10D8U)
-#define DBSC_DBSCHQOS_10_3             (DBSC_BASE + 0x10DCU)
-#define DBSC_DBSCHQOS_11_0             (DBSC_BASE + 0x10E0U)
-#define DBSC_DBSCHQOS_11_1             (DBSC_BASE + 0x10E4U)
-#define DBSC_DBSCHQOS_11_2             (DBSC_BASE + 0x10E8U)
-#define DBSC_DBSCHQOS_11_3             (DBSC_BASE + 0x10ECU)
-#define DBSC_DBSCHQOS_12_0             (DBSC_BASE + 0x10F0U)
-#define DBSC_DBSCHQOS_12_1             (DBSC_BASE + 0x10F4U)
-#define DBSC_DBSCHQOS_12_2             (DBSC_BASE + 0x10F8U)
-#define DBSC_DBSCHQOS_12_3             (DBSC_BASE + 0x10FCU)
-#define DBSC_DBSCHQOS_13_0             (DBSC_BASE + 0x1100U)
-#define DBSC_DBSCHQOS_13_1             (DBSC_BASE + 0x1104U)
-#define DBSC_DBSCHQOS_13_2             (DBSC_BASE + 0x1108U)
-#define DBSC_DBSCHQOS_13_3             (DBSC_BASE + 0x110CU)
-#define DBSC_DBSCHQOS_14_0             (DBSC_BASE + 0x1110U)
-#define DBSC_DBSCHQOS_14_1             (DBSC_BASE + 0x1114U)
-#define DBSC_DBSCHQOS_14_2             (DBSC_BASE + 0x1118U)
-#define DBSC_DBSCHQOS_14_3             (DBSC_BASE + 0x111CU)
-#define DBSC_DBSCHQOS_15_0             (DBSC_BASE + 0x1120U)
-#define DBSC_DBSCHQOS_15_1             (DBSC_BASE + 0x1124U)
-#define DBSC_DBSCHQOS_15_2             (DBSC_BASE + 0x1128U)
-#define DBSC_DBSCHQOS_15_3             (DBSC_BASE + 0x112CU)
-#define DBSC_SCFCTST2                  (DBSC_BASE + 0x170CU)
-
-#define        AXI_BASE                        (0xE6784000U)
-#define        AXI_ADSPLCR0                    (AXI_BASE + 0x0008U)
-#define        AXI_ADSPLCR1                    (AXI_BASE + 0x000CU)
-#define        AXI_ADSPLCR2                    (AXI_BASE + 0x0010U)
-#define        AXI_ADSPLCR3                    (AXI_BASE + 0x0014U)
-#define        ADSPLCR0_ADRMODE_DEFAULT        ((uint32_t)0U << 31U)
-#define        ADSPLCR0_ADRMODE_GEN2           ((uint32_t)1U << 31U)
-#define        ADSPLCR0_SPLITSEL(x)            ((uint32_t)(x) << 16U)
-#define        ADSPLCR0_AREA(x)                ((uint32_t)(x) <<  8U)
-#define        ADSPLCR0_SWP                    (0x0CU)
-
-#define        MSTAT_BASE                      (0xE67E0000U)
-#define        MSTAT_FIX_QOS_BANK0             (MSTAT_BASE + 0x0000U)
-#define        MSTAT_FIX_QOS_BANK1             (MSTAT_BASE + 0x1000U)
-#define        MSTAT_BE_QOS_BANK0              (MSTAT_BASE + 0x2000U)
-#define        MSTAT_BE_QOS_BANK1              (MSTAT_BASE + 0x3000U)
-#define        MSTAT_SL_INIT                   (MSTAT_BASE + 0x8000U)
-#define        MSTAT_REF_ARS                   (MSTAT_BASE + 0x8004U)
-#define        MSTAT_STATQC                    (MSTAT_BASE + 0x8008U)
-
-#define        RALLOC_BASE                     (0xE67F0000U)
-#define        RALLOC_RAS                      (RALLOC_BASE + 0x0000U)
-#define        RALLOC_FIXTH                    (RALLOC_BASE + 0x0004U)
-#define        RALLOC_RAEN                     (RALLOC_BASE + 0x0018U)
-#define        RALLOC_REGGD                    (RALLOC_BASE + 0x0020U)
-#define        RALLOC_DANN                     (RALLOC_BASE + 0x0030U)
-#define        RALLOC_DANT                     (RALLOC_BASE + 0x0038U)
-#define        RALLOC_EC                       (RALLOC_BASE + 0x003CU)
-#define        RALLOC_EMS                      (RALLOC_BASE + 0x0040U)
-#define        RALLOC_INSFC                    (RALLOC_BASE + 0x0050U)
-#define        RALLOC_BERR                     (RALLOC_BASE + 0x0054U)
-#define        RALLOC_RACNT0                   (RALLOC_BASE + 0x0080U)
-
 #if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
 static const mstat_slot_t mstat_fix[] = {
        {0x0000U, 0x0000000000000000UL},
@@ -394,70 +268,70 @@ static void dbsc_setting(void)
        }
 
        /* QoS Settings */
-       io_write_32(DBSC_DBSCHQOS_0_0, 0x0000F000);
-       io_write_32(DBSC_DBSCHQOS_0_1, 0x0000E000);
-       io_write_32(DBSC_DBSCHQOS_0_2, 0x00007000);
-       io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
-       /* DBSC_DBSCHQOS_1_0 not set */
-       /* DBSC_DBSCHQOS_1_1 not set */
-       /* DBSC_DBSCHQOS_1_2 not set */
-       /* DBSC_DBSCHQOS_1_3 not set */
-       /* DBSC_DBSCHQOS_2_0 not set */
-       /* DBSC_DBSCHQOS_2_1 not set */
-       /* DBSC_DBSCHQOS_2_2 not set */
-       /* DBSC_DBSCHQOS_2_3 not set */
-       /* DBSC_DBSCHQOS_3_0 not set */
-       /* DBSC_DBSCHQOS_3_1 not set */
-       /* DBSC_DBSCHQOS_3_2 not set */
-       /* DBSC_DBSCHQOS_3_3 not set */
-       io_write_32(DBSC_DBSCHQOS_4_0, 0x00000E00);
-       io_write_32(DBSC_DBSCHQOS_4_1, 0x00000DFF);
-       io_write_32(DBSC_DBSCHQOS_4_2, 0x00000400);
-       io_write_32(DBSC_DBSCHQOS_4_3, 0x00000200);
-       /* DBSC_DBSCHQOS_5_0 not set */
-       /* DBSC_DBSCHQOS_5_1 not set */
-       /* DBSC_DBSCHQOS_5_2 not set */
-       /* DBSC_DBSCHQOS_5_3 not set */
-       /* DBSC_DBSCHQOS_6_0 not set */
-       /* DBSC_DBSCHQOS_6_1 not set */
-       /* DBSC_DBSCHQOS_6_2 not set */
-       /* DBSC_DBSCHQOS_6_3 not set */
-       /* DBSC_DBSCHQOS_7_0 not set */
-       /* DBSC_DBSCHQOS_7_1 not set */
-       /* DBSC_DBSCHQOS_7_2 not set */
-       /* DBSC_DBSCHQOS_7_3 not set */
-       /* DBSC_DBSCHQOS_8_0 not set */
-       /* DBSC_DBSCHQOS_8_1 not set */
-       /* DBSC_DBSCHQOS_8_2 not set */
-       /* DBSC_DBSCHQOS_8_3 not set */
-       io_write_32(DBSC_DBSCHQOS_9_0, 0x00000C00);
-       io_write_32(DBSC_DBSCHQOS_9_1, 0x00000BFF);
-       io_write_32(DBSC_DBSCHQOS_9_2, 0x00000400);
-       io_write_32(DBSC_DBSCHQOS_9_3, 0x00000200);
-       /* DBSC_DBSCHQOS_10_0 not set */
-       /* DBSC_DBSCHQOS_10_1 not set */
-       /* DBSC_DBSCHQOS_10_2 not set */
-       /* DBSC_DBSCHQOS_10_3 not set */
-       /* DBSC_DBSCHQOS_11_0 not set */
-       /* DBSC_DBSCHQOS_11_1 not set */
-       /* DBSC_DBSCHQOS_11_2 not set */
-       /* DBSC_DBSCHQOS_11_3 not set */
-       /* DBSC_DBSCHQOS_12_0 not set */
-       /* DBSC_DBSCHQOS_12_1 not set */
-       /* DBSC_DBSCHQOS_12_2 not set */
-       /* DBSC_DBSCHQOS_12_3 not set */
-       io_write_32(DBSC_DBSCHQOS_13_0, 0x00000980);
-       io_write_32(DBSC_DBSCHQOS_13_1, 0x0000097F);
-       io_write_32(DBSC_DBSCHQOS_13_2, 0x00000300);
-       io_write_32(DBSC_DBSCHQOS_13_3, 0x00000180);
-       io_write_32(DBSC_DBSCHQOS_14_0, 0x00000800);
-       io_write_32(DBSC_DBSCHQOS_14_1, 0x000007FF);
-       io_write_32(DBSC_DBSCHQOS_14_2, 0x00000300);
-       io_write_32(DBSC_DBSCHQOS_14_3, 0x00000180);
-       io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0);
-       io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF);
-       io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0);
-       io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0);
+       io_write_32(DBSC_DBSCHQOS00, 0x0000F000);
+       io_write_32(DBSC_DBSCHQOS01, 0x0000E000);
+       io_write_32(DBSC_DBSCHQOS02, 0x00007000);
+       io_write_32(DBSC_DBSCHQOS03, 0x00000000);
+       /* DBSC_DBSCHQOS10 not set */
+       /* DBSC_DBSCHQOS11 not set */
+       /* DBSC_DBSCHQOS12 not set */
+       /* DBSC_DBSCHQOS13 not set */
+       /* DBSC_DBSCHQOS20 not set */
+       /* DBSC_DBSCHQOS21 not set */
+       /* DBSC_DBSCHQOS22 not set */
+       /* DBSC_DBSCHQOS23 not set */
+       /* DBSC_DBSCHQOS30 not set */
+       /* DBSC_DBSCHQOS31 not set */
+       /* DBSC_DBSCHQOS32 not set */
+       /* DBSC_DBSCHQOS33 not set */
+       io_write_32(DBSC_DBSCHQOS40, 0x00000E00);
+       io_write_32(DBSC_DBSCHQOS41, 0x00000DFF);
+       io_write_32(DBSC_DBSCHQOS42, 0x00000400);
+       io_write_32(DBSC_DBSCHQOS43, 0x00000200);
+       /* DBSC_DBSCHQOS50 not set */
+       /* DBSC_DBSCHQOS51 not set */
+       /* DBSC_DBSCHQOS52 not set */
+       /* DBSC_DBSCHQOS53 not set */
+       /* DBSC_DBSCHQOS60 not set */
+       /* DBSC_DBSCHQOS61 not set */
+       /* DBSC_DBSCHQOS62 not set */
+       /* DBSC_DBSCHQOS63 not set */
+       /* DBSC_DBSCHQOS70 not set */
+       /* DBSC_DBSCHQOS71 not set */
+       /* DBSC_DBSCHQOS72 not set */
+       /* DBSC_DBSCHQOS73 not set */
+       /* DBSC_DBSCHQOS80 not set */
+       /* DBSC_DBSCHQOS81 not set */
+       /* DBSC_DBSCHQOS82 not set */
+       /* DBSC_DBSCHQOS83 not set */
+       io_write_32(DBSC_DBSCHQOS90, 0x00000C00);
+       io_write_32(DBSC_DBSCHQOS91, 0x00000BFF);
+       io_write_32(DBSC_DBSCHQOS92, 0x00000400);
+       io_write_32(DBSC_DBSCHQOS93, 0x00000200);
+       /* DBSC_DBSCHQOS100 not set */
+       /* DBSC_DBSCHQOS101 not set */
+       /* DBSC_DBSCHQOS102 not set */
+       /* DBSC_DBSCHQOS103 not set */
+       /* DBSC_DBSCHQOS110 not set */
+       /* DBSC_DBSCHQOS111 not set */
+       /* DBSC_DBSCHQOS112 not set */
+       /* DBSC_DBSCHQOS113 not set */
+       /* DBSC_DBSCHQOS120 not set */
+       /* DBSC_DBSCHQOS121 not set */
+       /* DBSC_DBSCHQOS122 not set */
+       /* DBSC_DBSCHQOS123 not set */
+       io_write_32(DBSC_DBSCHQOS130, 0x00000980);
+       io_write_32(DBSC_DBSCHQOS131, 0x0000097F);
+       io_write_32(DBSC_DBSCHQOS132, 0x00000300);
+       io_write_32(DBSC_DBSCHQOS133, 0x00000180);
+       io_write_32(DBSC_DBSCHQOS140, 0x00000800);
+       io_write_32(DBSC_DBSCHQOS141, 0x000007FF);
+       io_write_32(DBSC_DBSCHQOS142, 0x00000300);
+       io_write_32(DBSC_DBSCHQOS143, 0x00000180);
+       io_write_32(DBSC_DBSCHQOS150, 0x000007D0);
+       io_write_32(DBSC_DBSCHQOS151, 0x000007CF);
+       io_write_32(DBSC_DBSCHQOS152, 0x000005D0);
+       io_write_32(DBSC_DBSCHQOS153, 0x000003D0);
 }
 
 void qos_init_h3_v11(void)
@@ -499,44 +373,44 @@ void qos_init_h3_v11(void)
 
        /* Resource Alloc setting */
 #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
-       io_write_32(RALLOC_RAS, 0x00000020U);
+       io_write_32(QOSCTRL_RAS, 0x00000020U);
 #else
-       io_write_32(RALLOC_RAS, 0x00000040U);
+       io_write_32(QOSCTRL_RAS, 0x00000040U);
 #endif
-       io_write_32(RALLOC_FIXTH, 0x000F0005U);
-       io_write_32(RALLOC_REGGD, 0x00000000U);
+       io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
+       io_write_32(QOSCTRL_REGGD, 0x00000000U);
 #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
-       io_write_64(RALLOC_DANN, 0x0101010102020201UL);
-       io_write_32(RALLOC_DANT, 0x00181008U);
+       io_write_64(QOSCTRL_DANN, 0x0101010102020201UL);
+       io_write_32(QOSCTRL_DANT, 0x00181008U);
 #else
-       io_write_64(RALLOC_DANN, 0x0101000004040401UL);
-       io_write_32(RALLOC_DANT, 0x003C2010U);
+       io_write_64(QOSCTRL_DANN, 0x0101000004040401UL);
+       io_write_32(QOSCTRL_DANT, 0x003C2010U);
 #endif
-       io_write_32(RALLOC_EC, 0x00080001U);    /* need for H3 v1.* */
-       io_write_64(RALLOC_EMS, 0x0000000000000000UL);
-       io_write_32(RALLOC_INSFC, 0xC7840001U);
-       io_write_32(RALLOC_BERR, 0x00000000U);
-       io_write_32(RALLOC_RACNT0, 0x00000000U);
-
-       /* MSTAT setting */
-       io_write_32(MSTAT_SL_INIT,
+       io_write_32(QOSCTRL_EC, 0x00080001U);   /* need for H3 v1.* */
+       io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
+       io_write_32(QOSCTRL_INSFC, 0xC7840001U);
+       io_write_32(QOSCTRL_BERR, 0x00000000U);
+       io_write_32(QOSCTRL_RACNT0, 0x00000000U);
+
+       /* QOSBW setting */
+       io_write_32(QOSCTRL_SL_INIT,
                    SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
-       io_write_32(MSTAT_REF_ARS, 0x00330000U);
+       io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
 
-       /* MSTAT SRAM setting */
+       /* QOSBW SRAM setting */
        {
                uint32_t i;
 
                for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
-                       io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
+                       io_write_64(QOSBW_FIX_QOS_BANK0 + mstat_fix[i].addr,
                                    mstat_fix[i].value);
-                       io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
+                       io_write_64(QOSBW_FIX_QOS_BANK1 + mstat_fix[i].addr,
                                    mstat_fix[i].value);
                }
                for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
-                       io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
+                       io_write_64(QOSBW_BE_QOS_BANK0 + mstat_be[i].addr,
                                    mstat_be[i].value);
-                       io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
+                       io_write_64(QOSBW_BE_QOS_BANK1 + mstat_be[i].addr,
                                    mstat_be[i].value);
                }
        }
@@ -597,14 +471,14 @@ void qos_init_h3_v11(void)
        }
 
        /* Resource Alloc start */
-       io_write_32(RALLOC_RAEN, 0x00000001U);
+       io_write_32(QOSCTRL_RAEN, 0x00000001U);
 
-       /* MSTAT start */
-       io_write_32(MSTAT_STATQC, 0x00000001U);
+       /* QOSBW start */
+       io_write_32(QOSCTRL_STATQC, 0x00000001U);
 #else
        NOTICE("BL2: QoS is None\n");
 
        /* Resource Alloc setting */
-       io_write_32(RALLOC_EC, 0x00080001U);    /* need for H3 v1.* */
+       io_write_32(QOSCTRL_EC, 0x00080001U);   /* need for H3 v1.* */
 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
 }

diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
index c7137de55716b2471ac8e8847df791e1a54d5f0e..7592caa5ae6914f7567ecc5579b8376b43df46e7 100644 (file)
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
@@ -12,7 +12,6 @@
 #include "../qos_reg.h"
 #include "qos_init_h3_v20.h"
 
-
 #define        RCAR_QOS_VERSION                "rev.0.21"
 
 #define QOSWT_TIME_BANK0                               (20000000U)     /* unit:ns */

diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
index ffc9025c2277faa35928f1876357a7b026a229ae..1261a43089991a7803ccc3d5e024c1276c869ab7 100644 (file)
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
@@ -12,11 +12,8 @@
 #include "../qos_reg.h"
 #include "qos_init_h3_v30.h"
 
-
 #define        RCAR_QOS_VERSION                "rev.0.11"
 
-#define QOSCTRL_FSS                    (QOS_BASE1 + 0x0048U)
-
 #define QOSWT_TIME_BANK0                               (20000000U)     /* unit:ns */
 
 #define        QOSWT_WTEN_ENABLE                               (0x1U)

diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
index 6503b436c5747685e7fd1420599bcacb42769dee..0557b795084baf64776d6293f9051dbca5733edb 100644 (file)
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
@@ -12,11 +12,8 @@
 #include "../qos_reg.h"
 #include "qos_init_h3n_v30.h"
 
-
 #define        RCAR_QOS_VERSION                "rev.0.07"
 
-#define QOSCTRL_FSS                    (QOS_BASE1 + 0x0048U)
-
 #define QOSWT_TIME_BANK0                               (20000000U)     /* unit:ns */
 
 #define        QOSWT_WTEN_ENABLE                               (0x1U)

diff --git a/drivers/staging/renesas/rcar/qos/qos_reg.h b/drivers/staging/renesas/rcar/qos/qos_reg.h
index 759816fdc87eeaad11a28c54e9801f0bc6085d7d..cc0ea558aedd59ca8a9589546e7c3515b8b5f7cd 100644 (file)
--- a/drivers/staging/renesas/rcar/qos/qos_reg.h
+++ b/drivers/staging/renesas/rcar/qos/qos_reg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,12 +19,15 @@
 
 #define        DBSC_BASE                                       (0xE6790000U)
 #define DBSC_DBSYSCNT0                         (DBSC_BASE + 0x0100U)
+#define DBSC_AXARB                             (DBSC_BASE + 0x0800U)
 #define DBSC_DBCAM0CNF1                                (DBSC_BASE + 0x0904U)
 #define DBSC_DBCAM0CNF2                                (DBSC_BASE + 0x0908U)
 #define DBSC_DBCAM0CNF3                                (DBSC_BASE + 0x090CU)
 #define DBSC_DBSCHCNT0                         (DBSC_BASE + 0x1000U)
+#define DBSC_DBSCHCNT1                         (DBSC_BASE + 0x1004U)
 #define DBSC_DBSCHSZ0                          (DBSC_BASE + 0x1010U)
 #define DBSC_DBSCHRW0                          (DBSC_BASE + 0x1020U)
+#define DBSC_DBSCHRW1                          (DBSC_BASE + 0x1024U)
 #define DBSC_DBSCHQOS00                                (DBSC_BASE + 0x1030U)
 #define DBSC_DBSCHQOS01                                (DBSC_BASE + 0x1034U)
 #define DBSC_DBSCHQOS02                                (DBSC_BASE + 0x1038U)
@@ -53,6 +56,8 @@
 #define DBSC_DBSCHQOS151                       (DBSC_BASE + 0x1124U)
 #define DBSC_DBSCHQOS152                       (DBSC_BASE + 0x1128U)
 #define DBSC_DBSCHQOS153                       (DBSC_BASE + 0x112CU)
+#define DBSC_SCFCTST0                          (DBSC_BASE + 0x1700U)
+#define DBSC_SCFCTST1                          (DBSC_BASE + 0x1708U)
 #define DBSC_SCFCTST2                          (DBSC_BASE + 0x170CU)
 
 #define        AXI_BASE                                        (0xE6784000U)
@@ -80,11 +85,18 @@
 #define        QOSCTRL_STATQC                          (QOS_BASE0 + 0x8008U)
 
 #define        QOS_BASE1                                       (0xE67F0000U)
-#define        QOSCTRL_RAS                                     (QOS_BASE1 + 0x0000U)
+#define        QOSCTRL_RAS                             (QOS_BASE1 + 0x0000U)
+#define        QOSCTRL_FIXTH                           (QOS_BASE1 + 0x0004U)
 #define        QOSCTRL_RAEN                            (QOS_BASE1 + 0x0018U)
+#define        QOSCTRL_REGGD                           (QOS_BASE1 + 0x0020U)
 #define        QOSCTRL_DANN                            (QOS_BASE1 + 0x0030U)
 #define        QOSCTRL_DANT                            (QOS_BASE1 + 0x0038U)
+#define        QOSCTRL_EC                              (QOS_BASE1 + 0x003CU)
+#define        QOSCTRL_EMS                             (QOS_BASE1 + 0x0040U)
+#define        QOSCTRL_FSS                             (QOS_BASE1 + 0x0048U)
 #define        QOSCTRL_INSFC                           (QOS_BASE1 + 0x0050U)
+#define        QOSCTRL_BERR                            (QOS_BASE1 + 0x0054U)
+#define        QOSCTRL_EARLYR                          (QOS_BASE1 + 0x0060U)
 #define        QOSCTRL_RACNT0                          (QOS_BASE1 + 0x0080U)
 #define        QOSCTRL_STATGEN0                        (QOS_BASE1 + 0x0088U)