mmc: sdhci: pxav3: controller needs 32 bit ADMA addressing

Enable the quirk.

(Best used in conjunction with patch downgrading ADMA to SDMA when
transfer is not aligned.)

Signed-off-by: Philip Rakity <[email protected]>
Acked-by: Zhangfei Gao <[email protected]>
Signed-off-by: Chris Ball <[email protected]>

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 4198dbbc5c205f76c54e4b96c31a71901cf7f213..fc7e4a51562934064bf4345bbe0851461d011362 100644 (file)
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -195,7 +195,8 @@ static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
        clk_enable(clk);
 
        host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
-               | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
+               | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
+               | SDHCI_QUIRK_32BIT_ADMA_SIZE;
 
        /* enable 1/8V DDR capable */
        host->mmc->caps |= MMC_CAP_1_8V_DDR;