MIPS: Add definitions of SegCtl registers and use them

The SegCtl registers are standard for MIPSr3..MIPSr5. Add definitions of
these registers and use them rather than constants

Signed-off-by: Matt Redfearn <[email protected]>
Cc: Joshua Kinard <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Chris Packham <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/13290/
Signed-off-by: Ralf Baechle <[email protected]>

diff --git a/arch/mips/include/asm/mach-malta/kernel-entry-init.h b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
index 0cf8622db27f4689b9e7bb076b422d67a0c28cf9..ab03eb3fadac2e8959734d638050fee61678e9c9 100644 (file)
--- a/arch/mips/include/asm/mach-malta/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
@@ -56,7 +56,7 @@
                (0 << MIPS_SEGCFG_PA_SHIFT) |                           \
                (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
        or      t0, t2
-       mtc0    t0, $5, 2
+       mtc0    t0, CP0_SEGCTL0
 
        /* SegCtl1 */
        li      t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |      \
@@ -67,7 +67,7 @@
                (0 << MIPS_SEGCFG_PA_SHIFT) |                           \
                (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
        ins     t0, t1, 16, 3
-       mtc0    t0, $5, 3
+       mtc0    t0, CP0_SEGCTL1
 
        /* SegCtl2 */
        li      t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |      \
@@ -77,7 +77,7 @@
                (4 << MIPS_SEGCFG_PA_SHIFT) |                           \
                (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
        or      t0, t2
-       mtc0    t0, $5, 4
+       mtc0    t0, CP0_SEGCTL2
 
        jal     mips_ihb
        mfc0    t0, $16, 5

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 25d01577d0b564943f282960b67751e5bf84636a..8471905f92881a45f3ae81ca6c88f87ff6aa1ab6 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -48,6 +48,9 @@
 #define CP0_CONF $3
 #define CP0_CONTEXT $4
 #define CP0_PAGEMASK $5
+#define CP0_SEGCTL0 $5, 2
+#define CP0_SEGCTL1 $5, 3
+#define CP0_SEGCTL2 $5, 4
 #define CP0_WIRED $6
 #define CP0_INFO $7
 #define CP0_HWRENA $7, 0