clocksource/drivers/tegra: Fix IO endianness

Support big-endian kernel by using endian-aware register access
functions.

Signed-off-by: Dmitry Osipenko <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>

diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
index d2616ef167701526a13efe7ef896f3cca2c8668a..d8a3a4eb9f977961d9e8282422d7aa328c445057 100644 (file)
--- a/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -57,9 +57,9 @@ static u64 persistent_ms, last_persistent_ms;
 static struct delay_timer tegra_delay_timer;
 
 #define timer_writel(value, reg) \
-       __raw_writel(value, timer_reg_base + (reg))
+       writel_relaxed(value, timer_reg_base + (reg))
 #define timer_readl(reg) \
-       __raw_readl(timer_reg_base + (reg))
+       readl_relaxed(timer_reg_base + (reg))
 
 static int tegra_timer_set_next_event(unsigned long cycles,
                                         struct clock_event_device *evt)