plat: intel: Fix faulty DDR calibration value

A DDR calibration value is missing write mask, causing ECC DDR calibration
to fail. This patch addresses the issue. ECC should also be scrubbed before
MMU initializes, thus the scrubbing is moved to ddr intialization phase.

Signed-off-by: Loh Tien Hock <[email protected]>

diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c
index 2b40eefefb315e386ab8917e26a8f453f72f54a3..91e3b0ac51ee494de33ecfddeb9c5511011c18a0 100644 (file)
--- a/plat/intel/soc/stratix10/bl2_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl2_plat_setup.c
@@ -96,9 +96,6 @@ void bl2_el3_plat_arch_setup(void)
 
        enable_mmu_el3(0);
 
-       /* ECC Scrubbing */
-       memset(0, DRAM_BASE, DRAM_SIZE);
-
        dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000);
 
        info.mmc_dev_type = MMC_IS_SD;

diff --git a/plat/intel/soc/stratix10/include/s10_memory_controller.h b/plat/intel/soc/stratix10/include/s10_memory_controller.h
index f2a3e193898ab711ca255863d89e1928a4a627fd..ad7cb9db12656b2870946b4543a77d30ba0adb24 100644 (file)
--- a/plat/intel/soc/stratix10/include/s10_memory_controller.h
+++ b/plat/intel/soc/stratix10/include/s10_memory_controller.h
@@ -57,8 +57,11 @@
 #define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST      0
 #define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f)
 #define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST        0
+#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_MSK (BIT(0) | BIT(1))
 #define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST        2
+#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_MSK (BIT(2) | BIT(3))
 #define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST        4
+#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_MSK (BIT(4) | BIT(5))
 
 #define S10_MPFE_HMC_ADP(x)                    (0xf8011000 + (x))
 #define S10_MPFE_HMC_ADP_HPSINTFCSEL           0xf8011210

diff --git a/plat/intel/soc/stratix10/soc/s10_memory_controller.c b/plat/intel/soc/stratix10/soc/s10_memory_controller.c
index c528176e5ba84d64702be42e48b0d7e188b4bd94..851fc59a2eeb66b89d8837bd535eba086e7893ca 100644 (file)
--- a/plat/intel/soc/stratix10/soc/s10_memory_controller.c
+++ b/plat/intel/soc/stratix10/soc/s10_memory_controller.c
@@ -10,6 +10,7 @@
 #include <lib/mmio.h>
 #include <common/debug.h>
 #include <drivers/delay_timer.h>
+#include <platform_def.h>
 #include <string.h>
 
 #include "s10_memory_controller.h"
@@ -316,9 +317,15 @@ void configure_ddr_sched_ctrl_regs(void)
                act_to_act_bank << S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST);
 
        mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_DEVTODEV,
-       bus_rd_to_rd << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST |
-       bus_rd_to_wr << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST |
-       bus_wr_to_rd << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST);
+               ((bus_rd_to_rd
+                       << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST)
+                       & S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_MSK) |
+               ((bus_rd_to_wr
+                       << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST)
+                       & S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_MSK) |
+               ((bus_wr_to_rd
+                       << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST)
+                       & S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_MSK));
 
 }
 
@@ -393,7 +400,10 @@ void configure_hmc_adaptor_regs(void)
                        S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK |
                        S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK,
                        S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK);
+               INFO("Scrubbing ECC\n");
 
+               /* ECC Scrubbing */
+               memset(DRAM_BASE, 0, DRAM_SIZE);
        } else {
                INFO("ECC is disabled.\n");
        }