drm/i915/bdw: display stuff

Just enough to make the code not barf...

Init BDW display to look like HSW. For the simulator this should be
fine, but this will probably require more work.

Signed-off-by: Ben Widawsky <[email protected]>
[danvet: Add a FIXME comment about RCS flips being untested on bdw.
Also add a note that hblank events are reserved on bdw+ in DERRMR.]
Reviewed-by: Daniel Vetter <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f897a7092ce088ce2e0082eee31eadd990e46d75..48c3aef5acaa49e3daabf4f744a57af90ed6ede4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -743,6 +743,7 @@
 #define   FPGA_DBG_RM_NOCLAIM  (1<<31)
 
 #define DERRMR         0x44050
+/* Note that HBLANK events are reserved on bdw+ */
 #define   DERRMR_PIPEA_SCANLINE                (1<<0)
 #define   DERRMR_PIPEA_PRI_FLIP_DONE   (1<<1)
 #define   DERRMR_PIPEA_SPR_FLIP_DONE   (1<<2)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f34252d134b62bcd8cc72eecdbb592cc3761e543..d5eb5a4a9cf6f5eaf90dd46a4e1f142239c8a2d2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10309,7 +10309,7 @@ static void intel_init_display(struct drm_device *dev)
                        dev_priv->display.write_eld = ironlake_write_eld;
                        dev_priv->display.modeset_global_resources =
                                ivb_modeset_global_resources;
-               } else if (IS_HASWELL(dev)) {
+               } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
                        dev_priv->display.fdi_link_train = hsw_fdi_link_train;
                        dev_priv->display.write_eld = haswell_write_eld;
                        dev_priv->display.modeset_global_resources =
@@ -10340,6 +10340,7 @@ static void intel_init_display(struct drm_device *dev)
                dev_priv->display.queue_flip = intel_gen6_queue_flip;
                break;
        case 7:
+       case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
                dev_priv->display.queue_flip = intel_gen7_queue_flip;
                break;
        }

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 8afaad6bcc4821981a2843a843d2d69c33151dd4..f8b265c2b178dfa7dd7b03ef018f584747154c09 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1092,6 +1092,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
                break;
 
        case 7:
+       case 8:
                if (IS_IVYBRIDGE(dev)) {
                        intel_plane->can_scale = true;
                        intel_plane->max_downscale = 2;