rcar_gen3: drivers: ddr-a: Update E3 DDR setting

[IPL/DDR]
- Update E3 DDR setting rev.0.12.

Signed-off-by: Hiroyuki Nakano <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Change-Id: Ic9fb7ed1cd7588fab169a99c4070a8dfc40038dc

diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
index c289c88fd8b464e091be89bd4d5dbe32a6e72a15..544cadc83f6f9a7f31ee4270e2c8c97c4b6ea9a5 100644 (file)
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -100,12 +100,8 @@ uint32_t init_ddr(void)
 
 #if RCAR_DRAM_DDR3L_MEMCONF == 0
    WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); /*  1GB */
-#elif RCAR_DRAM_DDR3L_MEMCONF == 1
-   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /*  2GB(default) */
-#elif RCAR_DRAM_DDR3L_MEMCONF == 2
-   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02); /*  4GB */
 #else
-   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /*  2GB */
+   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /*  2GB(default) */
 #endif
 
 #if RCAR_DRAM_DDR3L_MEMDUAL == 1
@@ -894,10 +890,6 @@ uint32_t recovery_from_backup_mode(void)
 
 #if RCAR_DRAM_DDR3L_MEMCONF == 0
    WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02);
-#elif RCAR_DRAM_DDR3L_MEMCONF == 1
-   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02);
-#elif RCAR_DRAM_DDR3L_MEMCONF == 2
-   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02);
 #else
    WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02);
 #endif

diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
index 2e9a5bfc117b812e136a56f7a2646938bb17da58..1a96a69c7c7261f1e91bb60b71968ad7241be2a8 100644 (file)
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,7 +9,7 @@
 
 #include <stdint.h>
 
-#define RCAR_E3_DDR_VERSION    "rev.0.11"
+#define RCAR_E3_DDR_VERSION    "rev.0.12"
 
 #ifdef ddr_qos_init_setting
    #define REFRESH_RATE  3900               /*  Average periodic refresh interval[ns]. Support 3900,7800 */