cxl: Increase timeout for detection of AFU mmio hang

PSL designers recommend a larger value for the mmio hang pulse, 256 us
instead of 1 us. The CAIA architecture states that it needs to be
smaller than 1/2 of the RTOS timeout set in the PHB for outbound
non-posted transactions, which is still (easily) the case here.

Signed-off-by: Frederic Barrat <[email protected]>
Acked-by: Ian Munsie <[email protected]>
Tested-by: Frank Haverkamp <[email protected]>
Tested-by: Manoj Kumar <[email protected]>
Signed-off-by: Michael Ellerman <[email protected]>

diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index c6d5cf5e3793b60045a2bfa92b3ad0f9ca144ade..a08fcc888a71df37d4fcf6fd37d8716d71786d71 100644 (file)
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -375,8 +375,10 @@ static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev
                return -ENODEV;
        }
 
+       psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
+       psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
        /* Tell PSL where to route data to */
-       psl_dsnctl = 0x0000900002000000ULL | (chipid << (63-5));
+       psl_dsnctl |= (chipid << (63-5));
        psl_dsnctl |= (capp_unit_id << (63-13));
 
        cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);