MIPS: fix mips_cache fallback without __builtin_mips_cache

The "R" constraint supplies the address of an variable in a register. Use
"r" instead and adjust asm to supply the content of addr in a register
instead.

Fixes: 2b8bcc5a ("MIPS: avoid .set ISA for cache operations")
Signed-off-by: Matthias Schiffer <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>

diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index a3b07c6ad0d0c02a8cadb30ddc7f030927f7afea..002b839fd4cb016b41cb2272b1b0c6f9f6ec5635 100644 (file)
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -16,7 +16,7 @@ static inline void mips_cache(int op, const volatile void *addr)
 #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
        __builtin_mips_cache(op, addr);
 #else
-       __asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr));
+       __asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
 #endif
 }