MIPS: I6400: Icache fills from dcache

Coherence Manager 3 (CM3) as present in I6400 can fill icache lines
effectively from dirty dcaches, so there is no need to flush dirty lines
from dcaches through to L2 prior to icache invalidation.

Set the MIPS_CACHE_IC_F_DC flag such that cpu_has_ic_fills_f_dc
evaluates to true, which avoids those dcache flushes.

Signed-off-by: James Hogan <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: Manuel Lauss <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12180/
Signed-off-by: Ralf Baechle <[email protected]>

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index fc7289dfaf5adbbeebd3aa538d0ed67e9f12680d..69e7e5873af37d7bdc892f21a69a78fb23105477 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1311,6 +1311,7 @@ static void probe_pcache(void)
                break;
 
        case CPU_ALCHEMY:
+       case CPU_I6400:
                c->icache.flags |= MIPS_CACHE_IC_F_DC;
                break;