qualcommbe: ipq95xx: Refresh the NSSCC and PORT patch for new PCIe patches
authorChristian Marangi <[email protected]>
Thu, 30 Jan 2025 15:49:03 +0000 (16:49 +0100)
committerChristian Marangi <[email protected]>
Thu, 10 Apr 2025 13:01:10 +0000 (15:01 +0200)
Refresh the NSSCC patch for new PCIe patches. To keep track of fuzz
changes for the IPQ95xx patches, patch are not refreshed currently.

For the specific case of NSSCC patch, quilt gets confused and apply the
patch in the wrong node, putting it in the RPM node (causing all kind of
funny errors at runtime)

Correctly fix the patch to put the node right after the PCIe nodes.

Also the PORT patch need to be refreshed as the gpio header is added by
the PCIe patch.

Link: https://github.com/openwrt/openwrt/pull/17788
Signed-off-by: Christian Marangi <[email protected]>
target/linux/qualcommbe/patches-6.6/105-06-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch
target/linux/qualcommbe/patches-6.6/200-01-arm64-dts-qcom-ipq9574-Add-PCS-UNIPHY-device-tree-su.patch
target/linux/qualcommbe/patches-6.6/200-02-arm64-dts-qcom-Add-IPQ9574-MDIO-device-node.patch
target/linux/qualcommbe/patches-6.6/200-03-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch
target/linux/qualcommbe/patches-6.6/200-04-arm64-dts-qcom-Add-EDMA-node-for-IPQ9574.patch
target/linux/qualcommbe/patches-6.6/200-05-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch
target/linux/qualcommbe/patches-6.6/302-arm64-dts-qcom-Add-missing-clock-for-nsscc-from-pcs-.patch

index 3ec23307b0382c79f1c7922fb3ebb6225d188d6b..9aba070e63e16b31d38b9ceb4e104fc2222980c9 100644 (file)
@@ -22,11 +22,10 @@ Signed-off-by: Manikanta Mylavarapu <[email protected]>
  #include <dt-bindings/thermal/thermal.h>
  
  / {
-@@ -198,6 +200,26 @@
-                               qcom,glink-channels = "rpm_requests";
-                       };
+@@ -1216,6 +1218,25 @@
+                       status = "disabled";
                };
-+
 +              nsscc: clock-controller@39b00000 {
 +                      compatible = "qcom,ipq9574-nsscc";
 +                      reg = <0x39b00000 0x80000>;
@@ -48,4 +47,4 @@ Signed-off-by: Manikanta Mylavarapu <[email protected]>
 +              };
        };
  
-       reserved-memory {
+       thermal-zones {
index 4d0966d883b80382032ba5e16cc5854d0d6fd5d1..6867024ec16d91bbb51c058945c6cbd0e7ebcc65 100644 (file)
@@ -30,7 +30,7 @@ Signed-off-by: Lei Wei <[email protected]>
   */
  
  #include <dt-bindings/clock/qcom,apss-ipq.h>
-@@ -220,6 +220,114 @@
+@@ -1237,6 +1237,114 @@
                        #power-domain-cells = <1>;
                        #interconnect-cells = <1>;
                };
@@ -144,4 +144,4 @@ Signed-off-by: Lei Wei <[email protected]>
 +              };
        };
  
-       reserved-memory {
+       thermal-zones {
index d41a54810d8ae3989b54ad5342fbf05174604414..edfc1f649773384672dd5561a30567d3cc95d7a1 100644 (file)
@@ -15,7 +15,7 @@ Signed-off-by: Luo Jie <[email protected]>
 
 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
-@@ -425,6 +425,8 @@
+@@ -297,6 +297,8 @@
                mdio: mdio@90000 {
                        compatible =  "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
                        reg = <0x00090000 0x64>;
@@ -24,7 +24,7 @@ Signed-off-by: Luo Jie <[email protected]>
                        #address-cells = <1>;
                        #size-cells = <0>;
                        clocks = <&gcc GCC_MDIO_AHB_CLK>;
-@@ -542,6 +544,22 @@
+@@ -414,6 +416,22 @@
                        interrupt-controller;
                        #interrupt-cells = <2>;
  
index a99fe0129da02fb87f3b0d19ca1ef41fac4a03fc..3cad4008a94f01eebee5549b2188014bfbbc6e86 100644 (file)
@@ -15,11 +15,10 @@ Signed-off-by: Luo Jie <[email protected]>
 
 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
-@@ -328,6 +328,44 @@
-                                             "ch_tx";
-                       };
+@@ -1256,6 +1256,44 @@
+                       #interconnect-cells = <1>;
                };
-+
 +              ethernet@3a000000 {
 +                      compatible = "qcom,ipq9574-ppe";
 +                      reg = <0x3a000000 0xbef800>;
@@ -57,6 +56,7 @@ Signed-off-by: Luo Jie <[email protected]>
 +                                           "memnoc_nssnoc",
 +                                           "memnoc_nssnoc_1";
 +              };
-       };
-       reserved-memory {
++
+               pcsuniphy0: ethernet-uniphy@7a00000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
index 8b3bdc39f55ddeeed8a30d00d203ca64e3310134..b024a37e6b19beee7643ac45a6b05f32c5dada9e 100644 (file)
@@ -14,7 +14,7 @@ Signed-off-by: Pavithra R <[email protected]>
 
 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
-@@ -365,6 +365,74 @@
+@@ -1292,6 +1292,74 @@
                                             "nssnoc_memnoc",
                                             "memnoc_nssnoc",
                                             "memnoc_nssnoc_1";
@@ -87,5 +87,5 @@ Signed-off-by: Pavithra R <[email protected]>
 +                                                "edma_misc";
 +                      };
                };
-       };
  
+               pcsuniphy0: ethernet-uniphy@7a00000 {
index 5b093003d17cbee9200c646d5c46bfd2114598c9..daef80dd798faafaa14cec126bdbef915a4967de 100644 (file)
@@ -198,8 +198,8 @@ Signed-off-by: Lei Wei <[email protected]>
 +};
 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
-@@ -329,7 +329,7 @@
-                       };
+@@ -1256,7 +1256,7 @@
+                       #interconnect-cells = <1>;
                };
  
 -              ethernet@3a000000 {
index 111b71d401d31b36abf02e4419699e5feef4766b..f0d89d96e61917113372b2c1cb997675dea1a887 100644 (file)
@@ -21,7 +21,7 @@ Signed-off-by: Christian Marangi <[email protected]>
  #include <dt-bindings/thermal/thermal.h>
  
  / {
-@@ -208,12 +209,12 @@
+@@ -1243,12 +1244,12 @@
                                 <&cmn_pll NSS_1200MHZ_CLK>,
                                 <&cmn_pll PPE_353MHZ_CLK>,
                                 <&gcc GPLL0_OUT_AUX>,