KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch

Our routines look at tscdeadline and period when deciding state of a
timer.  The timer is disarmed when switching between TSC deadline and
other modes, so we should set everything to disarmed state.

Signed-off-by: Radim Krčmář <[email protected]>
Reviewed-by: Wanpeng Li <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 96ade848ae0b660c3fd534e5884ca58f2f277d2d..a778f1ae2927df889aa4416aba59ef676011ecbd 100644 (file)
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1330,8 +1330,10 @@ static void apic_update_lvtt(struct kvm_lapic *apic)
        if (apic->lapic_timer.timer_mode != timer_mode) {
                if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
                                APIC_LVT_TIMER_TSCDEADLINE)) {
-                       kvm_lapic_set_reg(apic, APIC_TMICT, 0);
                        hrtimer_cancel(&apic->lapic_timer.timer);
+                       kvm_lapic_set_reg(apic, APIC_TMICT, 0);
+                       apic->lapic_timer.period = 0;
+                       apic->lapic_timer.tscdeadline = 0;
                }
                apic->lapic_timer.timer_mode = timer_mode;
                limit_periodic_timer_frequency(apic);