rcar_gen3: drivers: qos: M3W: Drop MD pin check

The DBSC_SCFCTST2 is always written with the same value, no matter
what the MD pin value is, drop the entire check and just write the
register with the one and only possible value.

Signed-off-by: Marek Vasut <[email protected]>
Change-Id: Idf26cf064e99e95f0140dd747183efe6a6d7f0bf

diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
index 3acceeea95a1625c69f2b11d6e8bb80d9c30a6d8..5d6bd29cb762509f1314e4d6951e66f7beb04e33 100644 (file)
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
@@ -18,8 +18,6 @@
 
 static void dbsc_setting(void)
 {
-       uint32_t md = 0;
-
        /* BUFCAM settings */
        /* DBSC_DBCAM0CNF0 not set */
        io_write_32(DBSC_DBCAM0CNF1, 0x00043218);
@@ -30,26 +28,8 @@ static void dbsc_setting(void)
        io_write_32(DBSC_DBSCHSZ0, 0x00000001);
        io_write_32(DBSC_DBSCHRW0, 0x22421111);
 
-       md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
-
-       switch (md) {
-       case 0x0:
-               /* DDR3200 */
-               io_write_32(DBSC_SCFCTST2, 0x012F1123);
-               break;
-       case 0x1:               /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
-               /* DDR2800 */
-               io_write_32(DBSC_SCFCTST2, 0x012F1123);
-               break;
-       case 0x4:               /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
-               /* DDR2400 */
-               io_write_32(DBSC_SCFCTST2, 0x012F1123);
-               break;
-       default:                /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
-               /* DDR1600 */
-               io_write_32(DBSC_SCFCTST2, 0x012F1123);
-               break;
-       }
+       /* DDR3 */
+       io_write_32(DBSC_SCFCTST2, 0x012F1123);
 
        /* QoS Settings */
        io_write_32(DBSC_DBSCHQOS00, 0x00000F00);

diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
index 6ff21cc2cc184c6367d368005c668b537b2043c9..0dfd991003f733f64c322d982d30e0d3b2963ab6 100644 (file)
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
@@ -56,8 +56,6 @@
 
 static void dbsc_setting(void)
 {
-       uint32_t md = 0;
-
        /* BUFCAM settings */
        io_write_32(DBSC_DBCAM0CNF1, 0x00043218);
        io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
@@ -66,26 +64,8 @@ static void dbsc_setting(void)
        io_write_32(DBSC_DBSCHSZ0, 0x00000001);
        io_write_32(DBSC_DBSCHRW0, 0x22421111);
 
-       md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
-
-       switch (md) {
-       case 0x0:
-               /* DDR3200 */
-               io_write_32(DBSC_SCFCTST2, 0x012F1123);
-               break;
-       case 0x1:               /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
-               /* DDR2800 */
-               io_write_32(DBSC_SCFCTST2, 0x012F1123);
-               break;
-       case 0x4:               /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
-               /* DDR2400 */
-               io_write_32(DBSC_SCFCTST2, 0x012F1123);
-               break;
-       default:                /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
-               /* DDR1600 */
-               io_write_32(DBSC_SCFCTST2, 0x012F1123);
-               break;
-       }
+       /* DDR3 */
+       io_write_32(DBSC_SCFCTST2, 0x012F1123);
 
        /* QoS Settings */
        io_write_32(DBSC_DBSCHQOS00, 0x00000F00);

diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
index b82a942a727856556f5a422cd4bf1d78b2742164..4165a1e081ac4b9fbc33c66ec88a8ce72d496a09 100644 (file)
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
@@ -56,8 +56,6 @@
 
 static void dbsc_setting(void)
 {
-       uint32_t md=0;
-
        /* Register write enable */
        io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
 
@@ -69,26 +67,8 @@ static void dbsc_setting(void)
        io_write_32(DBSC_DBSCHSZ0,   0x00000001);
        io_write_32(DBSC_DBSCHRW0,   0x22421111);
 
-       md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17;
-
-       switch (md) {
-       case 0x0:
-               /* DDR3200 */
-               io_write_32(DBSC_SCFCTST2, 0x012F1123);
-               break;
-       case 0x1:       //MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4)
-               /* DDR2800 */
-               io_write_32(DBSC_SCFCTST2, 0x012F1123);
-               break;
-       case 0x4:       //MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4)
-               /* DDR2400 */
-               io_write_32(DBSC_SCFCTST2, 0x012F1123);
-               break;
-       default:        //MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4)
-               /* DDR1600 */
-               io_write_32(DBSC_SCFCTST2, 0x012F1123);
-               break;
-       }
+       /* DDR3 */
+       io_write_32(DBSC_SCFCTST2, 0x012F1123);
 
        /* QoS Settings */
        io_write_32(DBSC_DBSCHQOS00,  0x00000F00);