/* add port to switch mask of CPU_PORT */
priv->r->traffic_enable(priv->cpu_port, port);
- if (priv->is_lagmember[port]) {
+ if (priv->lag_non_primary & BIT_ULL(port)) {
pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
return 0;
}
if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev))
continue;
- if (join && priv->is_lagmember[other_port])
+ if (join && priv->lag_non_primary & BIT_ULL(other_port))
continue;
isolated = p->isolated && other_p->isolated;
pr_debug("%s %x: %d", __func__, (u32)priv, port);
- if (priv->is_lagmember[port]) {
+ if (priv->lag_non_primary & BIT_ULL(port)) {
pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
return 0;
}
int err = 0, idx;
u64 seed = priv->r->l2_hash_seed(mac, vid);
- if (priv->is_lagmember[port]) {
+ if (priv->lag_non_primary & BIT_ULL(port)) {
pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
return 0;
}
pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
- if (priv->is_lagmember[port]) {
+ if (priv->lag_non_primary & BIT_ULL(port)) {
pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
return -EINVAL;
}
pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
- if (priv->is_lagmember[port]) {
+ if (priv->lag_non_primary & BIT_ULL(port)) {
pr_info("%s: %d is lag slave. ignore\n", __func__, port);
return 0;
}
if (priv->lag_primary[group] == -1)
priv->lag_primary[group] = port;
else
- priv->is_lagmember[port] = 1;
+ priv->lag_non_primary |= BIT_ULL(port);
- priv->lagmembers |= (1ULL << port);
+ priv->lagmembers |= BIT_ULL(port);
pr_debug("lag_members = %llX\n", priv->lagmembers);
err = rtl83xx_lag_add(priv->ds, group, port, info);
goto out;
}
pr_info("port_lag_del: group %d, port %d\n",group, port);
- priv->lagmembers &=~ (1ULL << port);
+ priv->lagmembers &= ~BIT_ULL(port);
priv->lag_primary[group] = -1;
- priv->is_lagmember[port] = 0;
+ priv->lag_non_primary &= ~BIT_ULL(port);
pr_debug("lag_members = %llX\n", priv->lagmembers);
err = rtl83xx_lag_del(priv->ds, group, port);
if (err) {