reg = <0x0 0x1fa20000 0x0 0x388>;
};
- syscon@1fbe3400 {
+ pbus_csr: syscon@1fbe3400 {
compatible = "airoha,en7581-pbus-csr", "syscon";
reg = <0x0 0x1fbe3400 0x0 0xff>;
};
<&scuclk EN7581_PCIE2_RST>;
reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
+ mediatek,pbus-csr = <&pbus_csr 0x0 0x4>;
+
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
<&scuclk EN7581_PCIE2_RST>;
reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
+ mediatek,pbus-csr = <&pbus_csr 0x8 0xc>;
+
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
--- /dev/null
+From 0e7a622da17da0042294860cdb7a2fac091d25b1 Mon Sep 17 00:00:00 2001
+Date: Wed, 8 Jan 2025 10:50:40 +0100
+Subject: [PATCH 1/6] PCI: mediatek-gen3: Rely on clk_bulk_prepare_enable() in
+ mtk_pcie_en7581_power_up()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Replace clk_bulk_prepare() and clk_bulk_enable() with
+clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() routine.
+
+---
+ drivers/pci/controller/pcie-mediatek-gen3.c | 14 +++-----------
+ 1 file changed, 3 insertions(+), 11 deletions(-)
+
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -907,12 +907,6 @@ static int mtk_pcie_en7581_power_up(stru
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
+
+- err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
+- if (err) {
+- dev_err(dev, "failed to prepare clock\n");
+- goto err_clk_prepare;
+- }
+-
+ val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) |
+ FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) |
+ FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) |
+@@ -925,17 +919,15 @@ static int mtk_pcie_en7581_power_up(stru
+ FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf);
+ writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG);
+
+- err = clk_bulk_enable(pcie->num_clks, pcie->clks);
++ err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
+ if (err) {
+ dev_err(dev, "failed to prepare clock\n");
+- goto err_clk_enable;
++ goto err_clk_prepare_enable;
+ }
+
+ return 0;
+
+-err_clk_enable:
+- clk_bulk_unprepare(pcie->num_clks, pcie->clks);
+-err_clk_prepare:
++err_clk_prepare_enable:
+ pm_runtime_put_sync(dev);
+ pm_runtime_disable(dev);
+ reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
--- /dev/null
+From e4c7dfd953f7618f0ccb70d87c1629634f306fab Mon Sep 17 00:00:00 2001
+Date: Wed, 8 Jan 2025 10:50:41 +0100
+Subject: [PATCH 2/6] PCI: mediatek-gen3: Move reset/assert callbacks in
+ .power_up()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+In order to make the code more readable, the reset_control_bulk_assert()
+function for PHY reset lines is moved to make it pair with
+reset_control_bulk_deassert() in mtk_pcie_power_up() and
+mtk_pcie_en7581_power_up(). The same change is done for
+reset_control_assert() used to assert MAC reset line.
+
+Introduce PCIE_MTK_RESET_TIME_US macro for the time needed to
+complete PCIe reset on MediaTek controller.
+
+---
+ drivers/pci/controller/pcie-mediatek-gen3.c | 28 +++++++++++++--------
+ 1 file changed, 18 insertions(+), 10 deletions(-)
+
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -120,6 +120,8 @@
+
+ #define MAX_NUM_PHY_RESETS 3
+
++#define PCIE_MTK_RESET_TIME_US 10
++
+ /* Time in ms needed to complete PCIe reset on EN7581 SoC */
+ #define PCIE_EN7581_RESET_TIME_MS 100
+
+@@ -875,9 +877,14 @@ static int mtk_pcie_en7581_power_up(stru
+ u32 val;
+
+ /*
+- * Wait for the time needed to complete the bulk assert in
+- * mtk_pcie_setup for EN7581 SoC.
++ * The controller may have been left out of reset by the bootloader
++ * so make sure that we get a clean start by asserting resets here.
+ */
++ reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
++ pcie->phy_resets);
++ reset_control_assert(pcie->mac_reset);
++
++ /* Wait for the time needed to complete the reset lines assert. */
+ mdelay(PCIE_EN7581_RESET_TIME_MS);
+
+ err = phy_init(pcie->phy);
+@@ -944,6 +951,15 @@ static int mtk_pcie_power_up(struct mtk_
+ struct device *dev = pcie->dev;
+ int err;
+
++ /*
++ * The controller may have been left out of reset by the bootloader
++ * so make sure that we get a clean start by asserting resets here.
++ */
++ reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
++ pcie->phy_resets);
++ reset_control_assert(pcie->mac_reset);
++ usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US);
++
+ /* PHY power on and enable pipe clock */
+ err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
+ if (err) {
+@@ -1016,14 +1032,6 @@ static int mtk_pcie_setup(struct mtk_gen
+ * counter since the bulk is shared.
+ */
+ reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
+- /*
+- * The controller may have been left out of reset by the bootloader
+- * so make sure that we get a clean start by asserting resets here.
+- */
+- reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
+-
+- reset_control_assert(pcie->mac_reset);
+- usleep_range(10, 20);
+
+ /* Don't touch the hardware registers before power up */
+ err = pcie->soc->power_up(pcie);
--- /dev/null
+From 0c9d2d2ef0d916b490a9222ed20ff4616fca876d Mon Sep 17 00:00:00 2001
+Date: Wed, 8 Jan 2025 10:50:42 +0100
+Subject: [PATCH 3/6] PCI: mediatek-gen3: Add comment about initialization
+ order in mtk_pcie_en7581_power_up()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add a comment in mtk_pcie_en7581_power_up() to clarify, unlike the other
+MediaTek Gen3 controllers, the Airoha EN7581 requires PHY initialization
+and power-on before PHY reset deassert.
+
+---
+ drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -887,6 +887,10 @@ static int mtk_pcie_en7581_power_up(stru
+ /* Wait for the time needed to complete the reset lines assert. */
+ mdelay(PCIE_EN7581_RESET_TIME_MS);
+
++ /*
++ * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
++ * requires PHY initialization and power-on before PHY reset deassert.
++ */
+ err = phy_init(pcie->phy);
+ if (err) {
+ dev_err(dev, "failed to initialize PHY\n");
--- /dev/null
+From 90d4e466c9ea2010f33880a36317a8486ccbe082 Mon Sep 17 00:00:00 2001
+Date: Wed, 8 Jan 2025 10:50:43 +0100
+Subject: [PATCH 4/6] PCI: mediatek-gen3: Move reset delay in
+ mtk_pcie_en7581_power_up()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal
+causing occasional PCIe link down issues. In order to overcome the
+problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and
+REG_RESET_CONTROL (0x834) registers available in the clock module
+running clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up().
+
+In order to make the code more readable, move the wait for the time
+needed to complete the PCIe reset from en7581_pci_enable() to
+mtk_pcie_en7581_power_up().
+
+Reduce reset timeout from 250ms to the standard PCIE_T_PVPERL_MS value
+(100ms) since it has no impact on the driver behavior.
+
+---
+ drivers/clk/clk-en7523.c | 1 -
+ drivers/pci/controller/pcie-mediatek-gen3.c | 7 +++++++
+ 2 files changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/clk-en7523.c
++++ b/drivers/clk/clk-en7523.c
+@@ -489,7 +489,6 @@ static int en7581_pci_enable(struct clk_
+ REG_PCI_CONTROL_PERSTOUT;
+ val = readl(np_base + REG_PCI_CONTROL);
+ writel(val | mask, np_base + REG_PCI_CONTROL);
+- msleep(250);
+
+ return 0;
+ }
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -936,6 +936,13 @@ static int mtk_pcie_en7581_power_up(stru
+ goto err_clk_prepare_enable;
+ }
+
++ /*
++ * Airoha EN7581 performs PCIe reset via clk callbacks since it has a
++ * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to
++ * complete the PCIe reset.
++ */
++ msleep(PCIE_T_PVPERL_MS);
++
+ return 0;
+
+ err_clk_prepare_enable:
--- /dev/null
+From c98bee18d0a094e37100c85effe5e161418f8644 Mon Sep 17 00:00:00 2001
+Date: Wed, 8 Jan 2025 10:50:44 +0100
+Subject: [PATCH 5/6] PCI: mediatek-gen3: Rely on msleep() in
+ mtk_pcie_en7581_power_up()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Since mtk_pcie_en7581_power_up() runs in non-atomic context, rely on
+msleep() routine instead of mdelay().
+
+---
+ drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -885,7 +885,7 @@ static int mtk_pcie_en7581_power_up(stru
+ reset_control_assert(pcie->mac_reset);
+
+ /* Wait for the time needed to complete the reset lines assert. */
+- mdelay(PCIE_EN7581_RESET_TIME_MS);
++ msleep(PCIE_EN7581_RESET_TIME_MS);
+
+ /*
+ * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
+@@ -913,7 +913,7 @@ static int mtk_pcie_en7581_power_up(stru
+ * Wait for the time needed to complete the bulk de-assert above.
+ * This time is specific for EN7581 SoC.
+ */
+- mdelay(PCIE_EN7581_RESET_TIME_MS);
++ msleep(PCIE_EN7581_RESET_TIME_MS);
+
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
--- /dev/null
+From 491cb9c5084790aafa02e843349492c284373231 Mon Sep 17 00:00:00 2001
+Date: Thu, 9 Jan 2025 00:30:45 +0100
+Subject: [PATCH 6/6] PCI: mediatek-gen3: Avoid PCIe resetting via PERST# for
+ Airoha EN7581 SoC
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Airoha EN7581 has a hw bug asserting/releasing PERST# signal causing
+occasional PCIe link down issues. In order to overcome the problem,
+PERST# signal is not asserted/released during device probe or
+suspend/resume phase and the PCIe block is reset using
+en7523_reset_assert() and en7581_pci_enable().
+
+Introduce flags field in the mtk_gen3_pcie_pdata struct in order to
+specify per-SoC capabilities.
+
+---
+ drivers/pci/controller/pcie-mediatek-gen3.c | 59 ++++++++++++++-------
+ 1 file changed, 41 insertions(+), 18 deletions(-)
+
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -127,10 +127,18 @@
+
+ struct mtk_gen3_pcie;
+
++enum mtk_gen3_pcie_flags {
++ SKIP_PCIE_RSTB = BIT(0), /* Skip PERST# assertion during device
++ * probing or suspend/resume phase to
++ * avoid hw bugs/issues.
++ */
++};
++
+ /**
+ * struct mtk_gen3_pcie_pdata - differentiate between host generations
+ * @power_up: pcie power_up callback
+ * @phy_resets: phy reset lines SoC data.
++ * @flags: pcie device flags.
+ */
+ struct mtk_gen3_pcie_pdata {
+ int (*power_up)(struct mtk_gen3_pcie *pcie);
+@@ -138,6 +146,7 @@ struct mtk_gen3_pcie_pdata {
+ const char *id[MAX_NUM_PHY_RESETS];
+ int num_resets;
+ } phy_resets;
++ u32 flags;
+ };
+
+ /**
+@@ -404,22 +413,33 @@ static int mtk_pcie_startup_port(struct
+ val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
+ writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG);
+
+- /* Assert all reset signals */
+- val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
+- val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
+- writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
+-
+ /*
+- * Described in PCIe CEM specification sections 2.2 (PERST# Signal)
+- * and 2.2.1 (Initial Power-Up (G3 to S0)).
+- * The deassertion of PERST# should be delayed 100ms (TPVPERL)
+- * for the power and clock to become stable.
++ * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal
++ * causing occasional PCIe link down. In order to overcome the issue,
++ * PCIE_RSTB signals are not asserted/released at this stage and the
++ * PCIe block is reset using en7523_reset_assert() and
++ * en7581_pci_enable().
+ */
+- msleep(100);
+-
+- /* De-assert reset signals */
+- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
+- writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
++ if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
++ /* Assert all reset signals */
++ val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
++ val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
++ PCIE_PE_RSTB;
++ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
++
++ /*
++ * Described in PCIe CEM specification revision 6.0.
++ *
++ * The deassertion of PERST# should be delayed 100ms (TPVPERL)
++ * for the power and clock to become stable.
++ */
++ msleep(PCIE_T_PVPERL_MS);
++
++ /* De-assert reset signals */
++ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
++ PCIE_PE_RSTB);
++ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
++ }
+
+ /* Check if the link is up or not */
+ err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
+@@ -1178,10 +1198,12 @@ static int mtk_pcie_suspend_noirq(struct
+ return err;
+ }
+
+- /* Pull down the PERST# pin */
+- val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
+- val |= PCIE_PE_RSTB;
+- writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
++ if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
++ /* Assert the PERST# pin */
++ val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
++ val |= PCIE_PE_RSTB;
++ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
++ }
+
+ dev_dbg(pcie->dev, "entered L2 states successfully");
+
+@@ -1232,6 +1254,7 @@ static const struct mtk_gen3_pcie_pdata
+ .id[2] = "phy-lane2",
+ .num_resets = 3,
+ },
++ .flags = SKIP_PCIE_RSTB,
+ };
+
+ static const struct of_device_id mtk_pcie_of_match[] = {
--- /dev/null
+From b6d7bb0d3bd74b491e2e6fd59c4d5110d06fd63b Mon Sep 17 00:00:00 2001
+Date: Sat, 1 Feb 2025 12:00:18 +0100
+Subject: [PATCH] PCI: mediatek-gen3: Remove leftover mac_reset assert for
+ Airoha EN7581 SoC
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Remove a leftover assert for mac_reset line in mtk_pcie_en7581_power_up().
+
+This is not harmful since EN7581 does not requires mac_reset and
+mac_reset is not defined in EN7581 device tree.
+
+Link: https://lore.kernel.org/r/20250201-pcie-en7581-remove-mac_reset-v2-1-a06786cdc683@kernel.org
+[kwilczynski: commit log]
+---
+ drivers/pci/controller/pcie-mediatek-gen3.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -902,7 +902,6 @@ static int mtk_pcie_en7581_power_up(stru
+ */
+ reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
+ pcie->phy_resets);
+- reset_control_assert(pcie->mac_reset);
+
+ /* Wait for the time needed to complete the reset lines assert. */
+ msleep(PCIE_EN7581_RESET_TIME_MS);
--- /dev/null
+From 249b78298078448a699c39356d27d8183af4b281 Mon Sep 17 00:00:00 2001
+Date: Tue, 25 Feb 2025 09:04:07 +0100
+Subject: [PATCH] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581
+ SoC
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Configure PBus base address and address mask to allow the hw
+to detect if a given address is accessible on PCIe controller.
+
+Fixes: f6ab898356dd ("PCI: mediatek-gen3: Add Airoha EN7581 support")
+---
+ drivers/pci/controller/pcie-mediatek-gen3.c | 28 ++++++++++++++++++++-
+ 1 file changed, 27 insertions(+), 1 deletion(-)
+
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -15,6 +15,7 @@
+ #include <linux/irqchip/chained_irq.h>
+ #include <linux/irqdomain.h>
+ #include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/msi.h>
+ #include <linux/of_device.h>
+@@ -24,6 +25,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/pm_domain.h>
+ #include <linux/pm_runtime.h>
++#include <linux/regmap.h>
+ #include <linux/reset.h>
+
+ #include "../pci.h"
+@@ -892,9 +894,13 @@ static int mtk_pcie_parse_port(struct mt
+
+ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
+ {
++ struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
+ struct device *dev = pcie->dev;
++ struct resource_entry *entry;
++ struct regmap *pbus_regmap;
++ u32 val, args[2], size;
++ resource_size_t addr;
+ int err;
+- u32 val;
+
+ /*
+ * The controller may have been left out of reset by the bootloader
+@@ -907,6 +913,26 @@ static int mtk_pcie_en7581_power_up(stru
+ msleep(PCIE_EN7581_RESET_TIME_MS);
+
+ /*
++ * Configure PBus base address and base address mask to allow the
++ * hw to detect if a given address is accessible on PCIe controller.
++ */
++ pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,
++ "mediatek,pbus-csr",
++ ARRAY_SIZE(args),
++ args);
++ if (IS_ERR(pbus_regmap))
++ return PTR_ERR(pbus_regmap);
++
++ entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
++ if (!entry)
++ return -ENODEV;
++
++ addr = entry->res->start - entry->offset;
++ regmap_write(pbus_regmap, args[0], lower_32_bits(addr));
++ size = lower_32_bits(resource_size(entry->res));
++ regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));
++
++ /*
+ * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
+ * requires PHY initialization and power-on before PHY reset deassert.
+ */
+++ /dev/null
-From 0e7a622da17da0042294860cdb7a2fac091d25b1 Mon Sep 17 00:00:00 2001
-Message-ID: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-Date: Wed, 8 Jan 2025 10:50:40 +0100
-Subject: [PATCH 1/6] PCI: mediatek-gen3: Rely on clk_bulk_prepare_enable() in
- mtk_pcie_en7581_power_up()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Replace clk_bulk_prepare() and clk_bulk_enable() with
-clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() routine.
-
----
- drivers/pci/controller/pcie-mediatek-gen3.c | 14 +++-----------
- 1 file changed, 3 insertions(+), 11 deletions(-)
-
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -907,12 +907,6 @@ static int mtk_pcie_en7581_power_up(stru
- pm_runtime_enable(dev);
- pm_runtime_get_sync(dev);
-
-- err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
-- if (err) {
-- dev_err(dev, "failed to prepare clock\n");
-- goto err_clk_prepare;
-- }
--
- val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) |
- FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) |
- FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) |
-@@ -925,17 +919,15 @@ static int mtk_pcie_en7581_power_up(stru
- FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf);
- writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG);
-
-- err = clk_bulk_enable(pcie->num_clks, pcie->clks);
-+ err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
- if (err) {
- dev_err(dev, "failed to prepare clock\n");
-- goto err_clk_enable;
-+ goto err_clk_prepare_enable;
- }
-
- return 0;
-
--err_clk_enable:
-- clk_bulk_unprepare(pcie->num_clks, pcie->clks);
--err_clk_prepare:
-+err_clk_prepare_enable:
- pm_runtime_put_sync(dev);
- pm_runtime_disable(dev);
- reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
+++ /dev/null
-From e4c7dfd953f7618f0ccb70d87c1629634f306fab Mon Sep 17 00:00:00 2001
-Message-ID: <e4c7dfd953f7618f0ccb70d87c1629634f306fab.1736960708.git.lorenzo@kernel.org>
-In-Reply-To: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-References: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-Date: Wed, 8 Jan 2025 10:50:41 +0100
-Subject: [PATCH 2/6] PCI: mediatek-gen3: Move reset/assert callbacks in
- .power_up()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-In order to make the code more readable, the reset_control_bulk_assert()
-function for PHY reset lines is moved to make it pair with
-reset_control_bulk_deassert() in mtk_pcie_power_up() and
-mtk_pcie_en7581_power_up(). The same change is done for
-reset_control_assert() used to assert MAC reset line.
-
-Introduce PCIE_MTK_RESET_TIME_US macro for the time needed to
-complete PCIe reset on MediaTek controller.
-
----
- drivers/pci/controller/pcie-mediatek-gen3.c | 28 +++++++++++++--------
- 1 file changed, 18 insertions(+), 10 deletions(-)
-
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -120,6 +120,8 @@
-
- #define MAX_NUM_PHY_RESETS 3
-
-+#define PCIE_MTK_RESET_TIME_US 10
-+
- /* Time in ms needed to complete PCIe reset on EN7581 SoC */
- #define PCIE_EN7581_RESET_TIME_MS 100
-
-@@ -875,9 +877,14 @@ static int mtk_pcie_en7581_power_up(stru
- u32 val;
-
- /*
-- * Wait for the time needed to complete the bulk assert in
-- * mtk_pcie_setup for EN7581 SoC.
-+ * The controller may have been left out of reset by the bootloader
-+ * so make sure that we get a clean start by asserting resets here.
- */
-+ reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
-+ pcie->phy_resets);
-+ reset_control_assert(pcie->mac_reset);
-+
-+ /* Wait for the time needed to complete the reset lines assert. */
- mdelay(PCIE_EN7581_RESET_TIME_MS);
-
- err = phy_init(pcie->phy);
-@@ -944,6 +951,15 @@ static int mtk_pcie_power_up(struct mtk_
- struct device *dev = pcie->dev;
- int err;
-
-+ /*
-+ * The controller may have been left out of reset by the bootloader
-+ * so make sure that we get a clean start by asserting resets here.
-+ */
-+ reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
-+ pcie->phy_resets);
-+ reset_control_assert(pcie->mac_reset);
-+ usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US);
-+
- /* PHY power on and enable pipe clock */
- err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
- if (err) {
-@@ -1016,14 +1032,6 @@ static int mtk_pcie_setup(struct mtk_gen
- * counter since the bulk is shared.
- */
- reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
-- /*
-- * The controller may have been left out of reset by the bootloader
-- * so make sure that we get a clean start by asserting resets here.
-- */
-- reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
--
-- reset_control_assert(pcie->mac_reset);
-- usleep_range(10, 20);
-
- /* Don't touch the hardware registers before power up */
- err = pcie->soc->power_up(pcie);
+++ /dev/null
-From 0c9d2d2ef0d916b490a9222ed20ff4616fca876d Mon Sep 17 00:00:00 2001
-Message-ID: <0c9d2d2ef0d916b490a9222ed20ff4616fca876d.1736960708.git.lorenzo@kernel.org>
-In-Reply-To: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-References: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-Date: Wed, 8 Jan 2025 10:50:42 +0100
-Subject: [PATCH 3/6] PCI: mediatek-gen3: Add comment about initialization
- order in mtk_pcie_en7581_power_up()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add a comment in mtk_pcie_en7581_power_up() to clarify, unlike the other
-MediaTek Gen3 controllers, the Airoha EN7581 requires PHY initialization
-and power-on before PHY reset deassert.
-
----
- drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -887,6 +887,10 @@ static int mtk_pcie_en7581_power_up(stru
- /* Wait for the time needed to complete the reset lines assert. */
- mdelay(PCIE_EN7581_RESET_TIME_MS);
-
-+ /*
-+ * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
-+ * requires PHY initialization and power-on before PHY reset deassert.
-+ */
- err = phy_init(pcie->phy);
- if (err) {
- dev_err(dev, "failed to initialize PHY\n");
+++ /dev/null
-From 90d4e466c9ea2010f33880a36317a8486ccbe082 Mon Sep 17 00:00:00 2001
-Message-ID: <90d4e466c9ea2010f33880a36317a8486ccbe082.1736960708.git.lorenzo@kernel.org>
-In-Reply-To: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-References: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-Date: Wed, 8 Jan 2025 10:50:43 +0100
-Subject: [PATCH 4/6] PCI: mediatek-gen3: Move reset delay in
- mtk_pcie_en7581_power_up()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal
-causing occasional PCIe link down issues. In order to overcome the
-problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and
-REG_RESET_CONTROL (0x834) registers available in the clock module
-running clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up().
-
-In order to make the code more readable, move the wait for the time
-needed to complete the PCIe reset from en7581_pci_enable() to
-mtk_pcie_en7581_power_up().
-
-Reduce reset timeout from 250ms to the standard PCIE_T_PVPERL_MS value
-(100ms) since it has no impact on the driver behavior.
-
----
- drivers/clk/clk-en7523.c | 1 -
- drivers/pci/controller/pcie-mediatek-gen3.c | 7 +++++++
- 2 files changed, 7 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/clk-en7523.c
-+++ b/drivers/clk/clk-en7523.c
-@@ -489,7 +489,6 @@ static int en7581_pci_enable(struct clk_
- REG_PCI_CONTROL_PERSTOUT;
- val = readl(np_base + REG_PCI_CONTROL);
- writel(val | mask, np_base + REG_PCI_CONTROL);
-- msleep(250);
-
- return 0;
- }
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -936,6 +936,13 @@ static int mtk_pcie_en7581_power_up(stru
- goto err_clk_prepare_enable;
- }
-
-+ /*
-+ * Airoha EN7581 performs PCIe reset via clk callbacks since it has a
-+ * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to
-+ * complete the PCIe reset.
-+ */
-+ msleep(PCIE_T_PVPERL_MS);
-+
- return 0;
-
- err_clk_prepare_enable:
+++ /dev/null
-From c98bee18d0a094e37100c85effe5e161418f8644 Mon Sep 17 00:00:00 2001
-Message-ID: <c98bee18d0a094e37100c85effe5e161418f8644.1736960708.git.lorenzo@kernel.org>
-In-Reply-To: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-References: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-Date: Wed, 8 Jan 2025 10:50:44 +0100
-Subject: [PATCH 5/6] PCI: mediatek-gen3: Rely on msleep() in
- mtk_pcie_en7581_power_up()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Since mtk_pcie_en7581_power_up() runs in non-atomic context, rely on
-msleep() routine instead of mdelay().
-
----
- drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -885,7 +885,7 @@ static int mtk_pcie_en7581_power_up(stru
- reset_control_assert(pcie->mac_reset);
-
- /* Wait for the time needed to complete the reset lines assert. */
-- mdelay(PCIE_EN7581_RESET_TIME_MS);
-+ msleep(PCIE_EN7581_RESET_TIME_MS);
-
- /*
- * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
-@@ -913,7 +913,7 @@ static int mtk_pcie_en7581_power_up(stru
- * Wait for the time needed to complete the bulk de-assert above.
- * This time is specific for EN7581 SoC.
- */
-- mdelay(PCIE_EN7581_RESET_TIME_MS);
-+ msleep(PCIE_EN7581_RESET_TIME_MS);
-
- pm_runtime_enable(dev);
- pm_runtime_get_sync(dev);
+++ /dev/null
-From 491cb9c5084790aafa02e843349492c284373231 Mon Sep 17 00:00:00 2001
-Message-ID: <491cb9c5084790aafa02e843349492c284373231.1736960708.git.lorenzo@kernel.org>
-In-Reply-To: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-References: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
-Date: Thu, 9 Jan 2025 00:30:45 +0100
-Subject: [PATCH 6/6] PCI: mediatek-gen3: Avoid PCIe resetting via PERST# for
- Airoha EN7581 SoC
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Airoha EN7581 has a hw bug asserting/releasing PERST# signal causing
-occasional PCIe link down issues. In order to overcome the problem,
-PERST# signal is not asserted/released during device probe or
-suspend/resume phase and the PCIe block is reset using
-en7523_reset_assert() and en7581_pci_enable().
-
-Introduce flags field in the mtk_gen3_pcie_pdata struct in order to
-specify per-SoC capabilities.
-
----
- drivers/pci/controller/pcie-mediatek-gen3.c | 59 ++++++++++++++-------
- 1 file changed, 41 insertions(+), 18 deletions(-)
-
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -127,10 +127,18 @@
-
- struct mtk_gen3_pcie;
-
-+enum mtk_gen3_pcie_flags {
-+ SKIP_PCIE_RSTB = BIT(0), /* Skip PERST# assertion during device
-+ * probing or suspend/resume phase to
-+ * avoid hw bugs/issues.
-+ */
-+};
-+
- /**
- * struct mtk_gen3_pcie_pdata - differentiate between host generations
- * @power_up: pcie power_up callback
- * @phy_resets: phy reset lines SoC data.
-+ * @flags: pcie device flags.
- */
- struct mtk_gen3_pcie_pdata {
- int (*power_up)(struct mtk_gen3_pcie *pcie);
-@@ -138,6 +146,7 @@ struct mtk_gen3_pcie_pdata {
- const char *id[MAX_NUM_PHY_RESETS];
- int num_resets;
- } phy_resets;
-+ u32 flags;
- };
-
- /**
-@@ -404,22 +413,33 @@ static int mtk_pcie_startup_port(struct
- val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
- writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG);
-
-- /* Assert all reset signals */
-- val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
-- val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
-- writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
--
- /*
-- * Described in PCIe CEM specification sections 2.2 (PERST# Signal)
-- * and 2.2.1 (Initial Power-Up (G3 to S0)).
-- * The deassertion of PERST# should be delayed 100ms (TPVPERL)
-- * for the power and clock to become stable.
-+ * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal
-+ * causing occasional PCIe link down. In order to overcome the issue,
-+ * PCIE_RSTB signals are not asserted/released at this stage and the
-+ * PCIe block is reset using en7523_reset_assert() and
-+ * en7581_pci_enable().
- */
-- msleep(100);
--
-- /* De-assert reset signals */
-- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
-- writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
-+ if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
-+ /* Assert all reset signals */
-+ val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
-+ val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
-+ PCIE_PE_RSTB;
-+ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
-+
-+ /*
-+ * Described in PCIe CEM specification revision 6.0.
-+ *
-+ * The deassertion of PERST# should be delayed 100ms (TPVPERL)
-+ * for the power and clock to become stable.
-+ */
-+ msleep(PCIE_T_PVPERL_MS);
-+
-+ /* De-assert reset signals */
-+ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
-+ PCIE_PE_RSTB);
-+ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
-+ }
-
- /* Check if the link is up or not */
- err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
-@@ -1178,10 +1198,12 @@ static int mtk_pcie_suspend_noirq(struct
- return err;
- }
-
-- /* Pull down the PERST# pin */
-- val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
-- val |= PCIE_PE_RSTB;
-- writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
-+ if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
-+ /* Assert the PERST# pin */
-+ val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
-+ val |= PCIE_PE_RSTB;
-+ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
-+ }
-
- dev_dbg(pcie->dev, "entered L2 states successfully");
-
-@@ -1232,6 +1254,7 @@ static const struct mtk_gen3_pcie_pdata
- .id[2] = "phy-lane2",
- .num_resets = 3,
- },
-+ .flags = SKIP_PCIE_RSTB,
- };
-
- static const struct of_device_id mtk_pcie_of_match[] = {
+++ /dev/null
-From ca4217f3117dceb2d01e179d02031a8758404624 Mon Sep 17 00:00:00 2001
-Message-ID: <ca4217f3117dceb2d01e179d02031a8758404624.1736961235.git.lorenzo@kernel.org>
-Date: Tue, 3 Sep 2024 23:14:02 +0200
-Subject: [PATCH] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581
- SoC
-
-Configure PBus base address and address mask in order to allow the hw
-detecting if a given address is on PCIE0, PCIE1 or PCIE2.
-
----
- drivers/pci/controller/pcie-mediatek-gen3.c | 29 ++++++++++++++++++++-
- 1 file changed, 28 insertions(+), 1 deletion(-)
-
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -15,6 +15,7 @@
- #include <linux/irqchip/chained_irq.h>
- #include <linux/irqdomain.h>
- #include <linux/kernel.h>
-+#include <linux/mfd/syscon.h>
- #include <linux/module.h>
- #include <linux/msi.h>
- #include <linux/of_device.h>
-@@ -24,6 +25,7 @@
- #include <linux/platform_device.h>
- #include <linux/pm_domain.h>
- #include <linux/pm_runtime.h>
-+#include <linux/regmap.h>
- #include <linux/reset.h>
-
- #include "../pci.h"
-@@ -122,6 +124,13 @@
-
- #define PCIE_MTK_RESET_TIME_US 10
-
-+#define PCIE_EN7581_PBUS_ADDR(_n) (0x00 + ((_n) << 3))
-+#define PCIE_EN7581_PBUS_ADDR_MASK(_n) (0x04 + ((_n) << 3))
-+#define PCIE_EN7581_PBUS_BASE_ADDR(_n) \
-+ ((_n) == 2 ? 0x28000000 : \
-+ (_n) == 1 ? 0x24000000 : 0x20000000)
-+#define PCIE_EN7581_PBUS_BASE_ADDR_MASK GENMASK(31, 26)
-+
- /* Time in ms needed to complete PCIe reset on EN7581 SoC */
- #define PCIE_EN7581_RESET_TIME_MS 100
-
-@@ -893,7 +902,8 @@ static int mtk_pcie_parse_port(struct mt
- static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
- {
- struct device *dev = pcie->dev;
-- int err;
-+ struct regmap *map;
-+ int err, slot;
- u32 val;
-
- /*
-@@ -907,6 +917,23 @@ static int mtk_pcie_en7581_power_up(stru
- /* Wait for the time needed to complete the reset lines assert. */
- msleep(PCIE_EN7581_RESET_TIME_MS);
-
-+ map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr");
-+ if (IS_ERR(map))
-+ return PTR_ERR(map);
-+
-+ /*
-+ * Configure PBus base address and address mask in order to allow the
-+ * hw detecting if a given address is on PCIE0, PCIE1 or PCIE2.
-+ */
-+ slot = of_get_pci_domain_nr(dev->of_node);
-+ if (slot < 0)
-+ return slot;
-+
-+ regmap_write(map, PCIE_EN7581_PBUS_ADDR(slot),
-+ PCIE_EN7581_PBUS_BASE_ADDR(slot));
-+ regmap_write(map, PCIE_EN7581_PBUS_ADDR_MASK(slot),
-+ PCIE_EN7581_PBUS_BASE_ADDR_MASK);
-+
- /*
- * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
- * requires PHY initialization and power-on before PHY reset deassert.
+++ /dev/null
-From c4defe43ce17a87e6341d126ba736d9f7ebdc541 Mon Sep 17 00:00:00 2001
-Message-ID: <c4defe43ce17a87e6341d126ba736d9f7ebdc541.1736962769.git.lorenzo@kernel.org>
-Date: Wed, 15 Jan 2025 18:36:26 +0100
-Subject: [PATCH] PCI: mediatek-gen3: Remove mac_reset assert leftover for
- Airoha EN7581 SoC.
-
-Remove a leftover assert for mac_reset line in mtk_pcie_en7581_power_up().
-This is not armful since EN7581 does not requires mac_reset and
-mac_reset is not defined in EN7581 device tree.
-
----
- drivers/pci/controller/pcie-mediatek-gen3.c | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -912,7 +912,6 @@ static int mtk_pcie_en7581_power_up(stru
- */
- reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
- pcie->phy_resets);
-- reset_control_assert(pcie->mac_reset);
-
- /* Wait for the time needed to complete the reset lines assert. */
- msleep(PCIE_EN7581_RESET_TIME_MS);
projects / openwrt / openwrt.git / commitdiff