perf/x86/amd/uncore: Set the thread mask for F17h L3 PMCs

Fill in the L3 performance event select register ThreadMask
bitfield, to enable per hardware thread accounting.

Signed-off-by: Kim Phillips <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Cc: <[email protected]>
Cc: Alexander Shishkin <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Borislav Petkov <[email protected]>
Cc: Gary Hook <[email protected]>
Cc: H. Peter Anvin <[email protected]>
Cc: Janakarajan Natarajan <[email protected]>
Cc: Jiri Olsa <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Martin Liska <[email protected]>
Cc: Namhyung Kim <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Pu Wen <[email protected]>
Cc: Stephane Eranian <[email protected]>
Cc: Suravee Suthikulpanit <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Vince Weaver <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index c2c4ae5fbbfcd4e49d8b7931ea4872edf7d1e79f..a6ea07f2aa8482d6ea0835b4a745245c039b352e 100644 (file)
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -202,15 +202,22 @@ static int amd_uncore_event_init(struct perf_event *event)
        hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
        hwc->idx = -1;
 
+       if (event->cpu < 0)
+               return -EINVAL;
+
        /*
         * SliceMask and ThreadMask need to be set for certain L3 events in
         * Family 17h. For other events, the two fields do not affect the count.
         */
-       if (l3_mask && is_llc_event(event))
-               hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK);
+       if (l3_mask && is_llc_event(event)) {
+               int thread = 2 * (cpu_data(event->cpu).cpu_core_id % 4);
 
-       if (event->cpu < 0)
-               return -EINVAL;
+               if (smp_num_siblings > 1)
+                       thread += cpu_data(event->cpu).apicid & 1;
+
+               hwc->config |= (1ULL << (AMD64_L3_THREAD_SHIFT + thread) &
+                               AMD64_L3_THREAD_MASK) | AMD64_L3_SLICE_MASK;
+       }
 
        uncore = event_to_amd_uncore(event);
        if (!uncore)