The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Signed-off-by: Russell King <[email protected]>
#ifdef CONFIG_CACHE_L2X0
/* Shared attribute override enable, 32K*8way */
- l2x0_init(IOMEM(0xf0002000), 0x00440000, 0xc2000fff);
+ l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
#endif
r8a7740_add_standard_devices_dt();
#ifdef CONFIG_CACHE_L2X0
/* Shared attribute override enable, 32K*8way */
- l2x0_init(IOMEM(0xf0002000), 0x00440000, 0xc2000fff);
+ l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
#endif
i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
#ifdef CONFIG_CACHE_L2X0
/* Shared attribute override enable, 64K*8way */
- l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
+ l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
#endif
}
#ifdef CONFIG_CACHE_L2X0
/* Shared attribute override enable, 64K*8way */
- l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
+ l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
#endif
i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
* Shared attribute override enable, 64K*16way
* don't call iounmap(base)
*/
- l2x0_init(base, 0x00470000, 0xc2000fff);
+ l2x0_init(base, 0x00400000, 0xc20f0fff);
}
#endif
{
#ifdef CONFIG_CACHE_L2X0
/* Shared attribute override enable, 64K*16way */
- l2x0_init(IOMEM(0xf0100000), 0x00470000, 0xc2000fff);
+ l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
#endif
r8a7779_pm_init();