The hardware offers a 4-bit register containing the number of host
channels. However, the values of these register mean 1-16 host channels,
not 0-15. Since the dwc2_hw_params struct stores the actual number of
host channels supported instead of the raw register value, it should be
5 bits wide instead of 4.
Before this commit, hardware with 16 host channels would overflow the
field, making it appear as 0 channels.
This bug was introduced in commit
9badec2 (staging: dwc2: interpret all
hwcfg and related register at init time).
Reported-by: Dinh Nguyen <[email protected]>
Signed-off-by: Matthijs Kooijman <[email protected]>
Acked-by: Paul Zimmerman <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
unsigned dev_token_q_depth:5;
unsigned max_transfer_size:26;
unsigned max_packet_count:11;
- unsigned host_channels:4;
+ unsigned host_channels:5;
unsigned hs_phy_type:2;
unsigned fs_phy_type:2;
unsigned i2c_enable:1;