clk: ingenic: Add missing flag for UDC clock

The UDC clock of the JZ4740 SoC can be gated, but the data structure
representing it was missing the CGU_CLK_GATE flag to make it work.

Signed-off-by: Paul Cercueil <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index bc073dd4470df3de79ccb2c66df4c84ab6110342..4479c102e8994bdb414038d117adc9544c971e6c 100644 (file)
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -161,7 +161,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
        },
 
        [JZ4740_CLK_UDC] = {
-               "udc", CGU_CLK_MUX | CGU_CLK_DIV,
+               "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
                .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
                .mux = { CGU_REG_CPCCR, 29, 1 },
                .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },