ret = rtcl_register_clkhw(clk_idx);
if (ret) {
pr_err("%s: Couldn't register %s clock\n",
- __func__, rtcl_clk_info[clk_idx].display_name);
+ __func__, rtcl_clk_info[clk_idx].display_name);
goto err_hw_unregister;
}
}
ret = of_clk_add_hw_provider(rtcl_ccu->np, rtcl_get_clkhw, rtcl_ccu);
if (ret) {
pr_err("%s: Couldn't register clock provider of %s\n",
- __func__, of_node_full_name(rtcl_ccu->np));
+ __func__, of_node_full_name(rtcl_ccu->np));
goto err_hw_unregister;
}
priv->lags_port_members[group] |= BIT_ULL(port);
pr_info("%s: Added port %d to LAG %d. Members now %016llx.\n",
- __func__, port, group, priv->lags_port_members[group]);
+ __func__, port, group, priv->lags_port_members[group]);
return 0;
}
priv->lags_port_members[group] &= ~BIT_ULL(port);
pr_info("%s: Removed port %d from LAG %d. Members now %016llx.\n",
- __func__, port, group, priv->lags_port_members[group]);
+ __func__, port, group, priv->lags_port_members[group]);
return 0;
}
u64 entry;
pr_debug("%s searching for %08llx vid %d with key %d, seed: %016llx\n",
- __func__, nh->mac, nh->rvid, key, seed);
+ __func__, nh->mac, nh->rvid, key, seed);
e.type = L2_UNICAST;
u64_to_ether_addr(nh->mac, &e.mac[0]);
rhl_for_each_entry_rcu(r, tmp, list, linkage) {
pr_debug("%s: Setting up fwding: ip %pI4, GW mac %016llx\n",
- __func__, &ip_addr, mac);
+ __func__, &ip_addr, mac);
/* Reads the ROUTING table entry associated with the route */
priv->r->route_read(r->id, r);
}
static int rtldsa_fib4_add(struct rtl838x_switch_priv *priv,
- struct fib_entry_notifier_info *info)
+ struct fib_entry_notifier_info *info)
{
struct net_device *ndev = fib_info_nh(info->fi, 0)->fib_nh_dev;
int vlan = is_vlan_dev(ndev) ? vlan_dev_vlan_id(ndev) : 0;
}
static int rtl83xx_netevent_event(struct notifier_block *this,
- unsigned long event, void *ptr)
+ unsigned long event, void *ptr)
{
struct rtl838x_switch_priv *priv;
struct net_device *dev;
net_work->gw_addr = *(__be32 *)n->primary_key;
pr_debug("%s: updating neighbour on port %d, mac %016llx\n",
- __func__, port, net_work->mac);
+ __func__, port, net_work->mac);
queue_work(priv->wq, &net_work->work);
if (err)
netdev_warn(dev, "failed to handle neigh update (err %d)\n", err);
if (fen_info->fi->fib_nh_is_v6) {
NL_SET_ERR_MSG_MOD(info->extack,
- "IPv6 gateway with IPv4 route is not supported");
+ "IPv6 gateway with IPv4 route is not supported");
kfree(fib_work);
return notifier_from_errno(-EINVAL);
}
};
static ssize_t rtl838x_common_read(char __user *buffer, size_t count,
- loff_t *ppos, unsigned int value)
+ loff_t *ppos, unsigned int value)
{
char *buf;
ssize_t len;
}
static ssize_t rtl838x_common_write(const char __user *buffer, size_t count,
- loff_t *ppos, unsigned int *value)
+ loff_t *ppos, unsigned int *value)
{
char b[32];
ssize_t len;
}
static ssize_t stp_state_read(struct file *filp, char __user *buffer, size_t count,
- loff_t *ppos)
+ loff_t *ppos)
{
struct rtl838x_port *p = filp->private_data;
struct dsa_switch *ds = p->dp->ds;
}
static ssize_t stp_state_write(struct file *filp, const char __user *buffer,
- size_t count, loff_t *ppos)
+ size_t count, loff_t *ppos)
{
struct rtl838x_port *p = filp->private_data;
u32 value;
};
static ssize_t drop_counter_read(struct file *filp, char __user *buffer, size_t count,
- loff_t *ppos)
+ loff_t *ppos)
{
struct rtl838x_switch_priv *priv = filp->private_data;
const char **d;
seq_puts(m, "L2_UNICAST\n");
seq_printf(m, " mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n",
- e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
- e->vid, e->rvid);
+ e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
+ e->vid, e->rvid);
seq_printf(m, " port %d age %d", e->port, e->age);
if (e->is_static)
seq_puts(m, "L2_MULTICAST\n");
seq_printf(m, " mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n",
- e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
- e->vid, e->rvid);
+ e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
+ e->vid, e->rvid);
}
if (e->type == IP4_MULTICAST || e->type == IP6_MULTICAST) {
seq_puts(m, (e->type == IP4_MULTICAST) ?
- "IP4_MULTICAST\n" : "IP6_MULTICAST\n");
+ "IP4_MULTICAST\n" : "IP6_MULTICAST\n");
seq_printf(m, " gip %08x sip %08x vid %u rvid %u\n",
- e->mc_gip, e->mc_sip, e->vid, e->rvid);
+ e->mc_gip, e->mc_sip, e->vid, e->rvid);
}
portmask = priv->r->read_mcast_pmask(e->mc_portmask_index);
};
static ssize_t age_out_read(struct file *filp, char __user *buffer, size_t count,
- loff_t *ppos)
+ loff_t *ppos)
{
struct rtl838x_port *p = filp->private_data;
struct dsa_switch *ds = p->dp->ds;
}
static ssize_t age_out_write(struct file *filp, const char __user *buffer,
- size_t count, loff_t *ppos)
+ size_t count, loff_t *ppos)
{
struct rtl838x_port *p = filp->private_data;
u32 value;
};
static ssize_t port_egress_rate_read(struct file *filp, char __user *buffer, size_t count,
- loff_t *ppos)
+ loff_t *ppos)
{
struct rtl838x_port *p = filp->private_data;
struct dsa_switch *ds = p->dp->ds;
}
static ssize_t port_egress_rate_write(struct file *filp, const char __user *buffer,
- size_t count, loff_t *ppos)
+ size_t count, loff_t *ppos)
{
struct rtl838x_port *p = filp->private_data;
struct dsa_switch *ds = p->dp->ds;
if (priv->family_id == RTL8380_FAMILY_ID) {
debugfs_create_x32("storm_rate_uc", 0644, port_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port)));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port)));
debugfs_create_x32("storm_rate_mc", 0644, port_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_MC(port)));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_MC(port)));
debugfs_create_x32("storm_rate_bc", 0644, port_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port)));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port)));
} else {
debugfs_create_x32("storm_rate_uc", 0644, port_dir,
- (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_UC_0(port)));
+ (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_UC_0(port)));
debugfs_create_x32("storm_rate_mc", 0644, port_dir,
- (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_MC_0(port)));
+ (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_MC_0(port)));
debugfs_create_x32("storm_rate_bc", 0644, port_dir,
- (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_BC_0(port)));
+ (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_BC_0(port)));
}
debugfs_create_u32("id", 0444, port_dir, (u32 *)&priv->ports[port].dp->index);
if (priv->family_id == RTL8380_FAMILY_ID) {
debugfs_create_x32("led_glb_ctrl", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_LED_GLB_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_LED_GLB_CTRL));
debugfs_create_x32("led_mode_sel", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_LED_MODE_SEL));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_LED_MODE_SEL));
debugfs_create_x32("led_mode_ctrl", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_LED_MODE_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_LED_MODE_CTRL));
debugfs_create_x32("led_p_en_ctrl", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_LED_P_EN_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_LED_P_EN_CTRL));
debugfs_create_x32("led_sw_ctrl", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_LED_SW_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_LED_SW_CTRL));
debugfs_create_x32("led0_sw_p_en_ctrl", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_LED0_SW_P_EN_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_LED0_SW_P_EN_CTRL));
debugfs_create_x32("led1_sw_p_en_ctrl", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_LED1_SW_P_EN_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_LED1_SW_P_EN_CTRL));
debugfs_create_x32("led2_sw_p_en_ctrl", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_LED2_SW_P_EN_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_LED2_SW_P_EN_CTRL));
for (int p = 0; p < 28; p++) {
char led_sw_p_ctrl_name[20];
snprintf(led_sw_p_ctrl_name, sizeof(led_sw_p_ctrl_name),
"led_sw_p_ctrl.%02d", p);
debugfs_create_x32(led_sw_p_ctrl_name, 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_LED_SW_P_CTRL_PORT(p)));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_LED_SW_P_CTRL_PORT(p)));
}
} else if (priv->family_id == RTL8390_FAMILY_ID) {
char port_led_name[20];
debugfs_create_x32("led_glb_ctrl", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_GLB_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_GLB_CTRL));
debugfs_create_x32("led_set_2_3", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_2_3_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_2_3_CTRL));
debugfs_create_x32("led_set_0_1", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_0_1_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_0_1_CTRL));
for (int p = 0; p < 4; p++) {
snprintf(port_led_name, sizeof(port_led_name), "led_copr_set_sel.%1d", p);
debugfs_create_x32(port_led_name, 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_SET_SEL_CTRL(p << 4)));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_SET_SEL_CTRL(p << 4)));
snprintf(port_led_name, sizeof(port_led_name), "led_fib_set_sel.%1d", p);
debugfs_create_x32(port_led_name, 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_SET_SEL_CTRL(p << 4)));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_SET_SEL_CTRL(p << 4)));
}
debugfs_create_x32("led_copr_pmask_ctrl_0", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(0)));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(0)));
debugfs_create_x32("led_copr_pmask_ctrl_1", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(32)));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(32)));
debugfs_create_x32("led_fib_pmask_ctrl_0", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(0)));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(0)));
debugfs_create_x32("led_fib_pmask_ctrl_1", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(32)));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(32)));
debugfs_create_x32("led_combo_ctrl_0", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(0)));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(0)));
debugfs_create_x32("led_combo_ctrl_1", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(32)));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(32)));
debugfs_create_x32("led_sw_ctrl", 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_CTRL));
for (int p = 0; p < 5; p++) {
snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_en_ctrl.%1d", p);
debugfs_create_x32(port_led_name, 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_EN_CTRL(p * 10)));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_EN_CTRL(p * 10)));
}
for (int p = 0; p < 28; p++) {
snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_ctrl.%02d", p);
debugfs_create_x32(port_led_name, 0644, led_dir,
- (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_CTRL(p)));
+ (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_CTRL(p)));
}
}
return 0;
snprintf(lag_name, sizeof(lag_name), "lag.%02d", i);
if (priv->family_id == RTL8380_FAMILY_ID)
debugfs_create_x32(lag_name, 0644, rtl838x_dir,
- (u32 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));
+ (u32 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));
else
debugfs_create_x64(lag_name, 0644, rtl838x_dir,
- (u64 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));
+ (u64 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));
}
/* Create directories for mirror groups */
mirror_dir = debugfs_create_dir(mirror_name, rtl838x_dir);
if (priv->family_id == RTL8380_FAMILY_ID) {
debugfs_create_x32("ctrl", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_CTRL + i * 4));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_CTRL + i * 4));
debugfs_create_x32("ingress_pm", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_SPM_CTRL + i * 4));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_SPM_CTRL + i * 4));
debugfs_create_x32("egress_pm", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_DPM_CTRL + i * 4));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_DPM_CTRL + i * 4));
debugfs_create_x32("qid", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_QID_CTRL(i)));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_QID_CTRL(i)));
debugfs_create_x32("rspan_vlan", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL(i)));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL(i)));
debugfs_create_x32("rspan_vlan_mac", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(i)));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(i)));
debugfs_create_x32("rspan_tx", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_CTRL));
debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL));
debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL));
} else {
debugfs_create_x32("ctrl", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_CTRL + i * 4));
+ (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_CTRL + i * 4));
debugfs_create_x64("ingress_pm", 0644, mirror_dir,
- (u64 *)(RTL838X_SW_BASE + RTL839X_MIR_SPM_CTRL + i * 8));
+ (u64 *)(RTL838X_SW_BASE + RTL839X_MIR_SPM_CTRL + i * 8));
debugfs_create_x64("egress_pm", 0644, mirror_dir,
- (u64 *)(RTL838X_SW_BASE + RTL839X_MIR_DPM_CTRL + i * 8));
+ (u64 *)(RTL838X_SW_BASE + RTL839X_MIR_DPM_CTRL + i * 8));
debugfs_create_x32("rspan_vlan", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_VLAN_CTRL(i)));
+ (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_VLAN_CTRL(i)));
debugfs_create_x32("rspan_tx", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_CTRL));
debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL));
debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir,
- (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL));
debugfs_create_x64("sample_rate", 0644, mirror_dir,
- (u64 *)(RTL838X_SW_BASE + RTL839X_MIR_SAMPLE_RATE_CTRL));
+ (u64 *)(RTL838X_SW_BASE + RTL839X_MIR_SAMPLE_RATE_CTRL));
}
}
if (priv->family_id == RTL8380_FAMILY_ID)
debugfs_create_x32("bpdu_flood_mask", 0644, rtl838x_dir,
- (u32 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));
+ (u32 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));
else
debugfs_create_x64("bpdu_flood_mask", 0644, rtl838x_dir,
- (u64 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));
+ (u64 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));
if (priv->family_id == RTL8380_FAMILY_ID)
debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir,
- (u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_CTRL));
else
debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir,
- (u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_CTRL));
+ (u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_CTRL));
ret = rtl838x_dbgfs_leds(rtl838x_dir, priv);
if (ret)
}
static void rtldsa_83xx_phylink_get_caps(struct dsa_switch *ds, int port,
- struct phylink_config *config)
+ struct phylink_config *config)
{
/*
* TODO: This needs to take into account the MAC to SERDES mapping and the
}
static void rtldsa_93xx_phylink_get_caps(struct dsa_switch *ds, int port,
- struct phylink_config *config)
+ struct phylink_config *config)
{
/*
* TODO: This needs to take into account the MAC to SERDES mapping and the
}
static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
- unsigned int mode,
+ unsigned int mode,
const struct phylink_link_state *state)
{
struct dsa_port *dp = dsa_to_port(ds, port);
}
static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
- unsigned int mode,
+ unsigned int mode,
const struct phylink_link_state *state)
{
struct rtl838x_switch_priv *priv = ds->priv;
}
static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
- unsigned int mode,
+ unsigned int mode,
const struct phylink_link_state *state)
{
struct rtl838x_switch_priv *priv = ds->priv;
}
static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
- unsigned int mode,
+ unsigned int mode,
phy_interface_t interface)
{
struct rtl838x_switch_priv *priv = ds->priv;
}
static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
- unsigned int mode,
+ unsigned int mode,
phy_interface_t interface)
{
struct rtl838x_switch_priv *priv = ds->priv;
}
static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
- unsigned int mode,
+ unsigned int mode,
phy_interface_t interface,
struct phy_device *phydev,
int speed, int duplex,
}
pr_debug("%s port %d, mode %x, speed %d, duplex %d, txpause %d, rxpause %d: set mcr=%08x\n",
- __func__, port, mode, speed, duplex, tx_pause, rx_pause, mcr);
+ __func__, port, mode, speed, duplex, tx_pause, rx_pause, mcr);
sw_w32(mcr, priv->r->mac_force_mode_ctrl(port));
/* Restart TX/RX to port */
}
static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
- unsigned int mode,
- phy_interface_t interface,
- struct phy_device *phydev,
- int speed, int duplex,
- bool tx_pause, bool rx_pause)
+ unsigned int mode,
+ phy_interface_t interface,
+ struct phy_device *phydev,
+ int speed, int duplex,
+ bool tx_pause, bool rx_pause)
{
struct dsa_port *dp = dsa_to_port(ds, port);
struct rtl838x_switch_priv *priv = ds->priv;
}
pr_debug("%s port %d, mode %x, speed %d, duplex %d, txpause %d, rxpause %d: set mcr=%08x\n",
- __func__, port, mode, speed, duplex, tx_pause, rx_pause, mcr);
+ __func__, port, mode, speed, duplex, tx_pause, rx_pause, mcr);
sw_w32(mcr, priv->r->mac_force_mode_ctrl(port));
/* Restart TX/RX to port */
{
struct rtl838x_switch_priv *priv = ds->priv;
- pr_debug("%s: %x %d", __func__, (u32) priv, port);
+ pr_debug("%s: %x %d", __func__, (u32)priv, port);
priv->ports[port].enable = true;
/* enable inner tagging on egress, do not keep any tags */
priv->r->vlan_tables_read(0, &info);
pr_debug("VLAN 0: Member ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
- info.member_ports, info.untagged_ports, info.profile_id,
- info.hash_mc_fid, info.hash_uc_fid, info.fid);
+ info.member_ports, info.untagged_ports, info.profile_id,
+ info.hash_mc_fid, info.hash_uc_fid, info.fid);
priv->r->vlan_tables_read(1, &info);
pr_debug("VLAN 1: Member ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
- info.member_ports, info.untagged_ports, info.profile_id,
- info.hash_mc_fid, info.hash_uc_fid, info.fid);
+ info.member_ports, info.untagged_ports, info.profile_id,
+ info.hash_mc_fid, info.hash_uc_fid, info.fid);
priv->r->vlan_set_untagged(1, info.untagged_ports);
pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
int err;
pr_debug("%s port %d, vid %d, flags %x\n",
- __func__, port, vlan->vid, vlan->flags);
+ __func__, port, vlan->vid, vlan->flags);
/* Let no one mess with our special VLAN 0 */
if (!vlan->vid)
u16 pvid;
pr_debug("%s: port %d, vid %d, flags %x\n",
- __func__, port, vlan->vid, vlan->flags);
+ __func__, port, vlan->vid, vlan->flags);
/* Let no one mess with our special VLAN 0 */
if (!vlan->vid)
* when no slots are available returns -1
*/
static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
- bool must_exist, struct rtl838x_l2_entry *e)
+ bool must_exist, struct rtl838x_l2_entry *e)
{
int idx = -1;
u32 key = priv->r->l2_hash_key(priv, seed);
if (idx >= 0) {
if (e.valid) {
pr_debug("Found an existing entry %016llx, mc_group %d\n",
- ether_addr_to_u64(e.mac), e.mc_portmask_index);
+ ether_addr_to_u64(e.mac), e.mc_portmask_index);
rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
} else {
pr_debug("New entry for seed %016llx\n", seed);
}
static int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
- const struct switchdev_obj_port_mdb *mdb,
+ const struct switchdev_obj_port_mdb *mdb,
const struct dsa_db db)
{
struct rtl838x_switch_priv *priv = ds->priv;
}
static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
- struct net_device *lag,
- struct netdev_lag_upper_info *info)
+ struct net_device *lag,
+ struct netdev_lag_upper_info *info)
{
int id;
}
static int rtl83xx_port_lag_join(struct dsa_switch *ds,
- int port,
- struct dsa_lag lag,
- struct netdev_lag_upper_info *info,
- struct netlink_ext_ack *extack)
+ int port,
+ struct dsa_lag lag,
+ struct netdev_lag_upper_info *info,
+ struct netlink_ext_ack *extack)
{
struct rtl838x_switch_priv *priv = ds->priv;
int err = 0;
* units of the rate is 16Kbps
*/
void rtl838x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port,
- int queue, u32 rate)
+ int queue, u32 rate)
{
if (port > priv->cpu_port)
return;
* units of the rate is 16Kbps
*/
static void rtl839x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port,
- int queue, u32 rate)
+ int queue, u32 rate)
{
int lsb = 128 + queue * 20;
int low_byte = 8 - (lsb >> 5);
u32 high_mask = 0xfffff >> (32 - start_bit);
pr_debug("%s: Setting egress rate on port %d, queue %d to %d\n",
- __func__, port, queue, rate);
+ __func__, port, queue, rate);
if (port >= priv->cpu_port)
return;
if (queue > 7)
}
static void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port,
- enum scheduler_type sched)
+ enum scheduler_type sched)
{
enum scheduler_type t = rtl839x_get_scheduling_algorithm(priv, port);
u32 v, oam_state, oam_port_state;
}
static void rtl839x_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv, int port,
- int *queue_weights)
+ int *queue_weights)
{
mutex_lock(&priv->reg_mutex);
int high_mask = 0x3ff >> (32 - start_bit);
sw_w32_mask(0x3ff << start_bit, (queue_weights[i] & 0x3ff) << start_bit,
- RTL839X_TBL_ACCESS_DATA_2(low_byte));
+ RTL839X_TBL_ACCESS_DATA_2(low_byte));
if (high_mask)
sw_w32_mask(high_mask, (queue_weights[i] & 0x3ff) >> (32 - start_bit),
- RTL839X_TBL_ACCESS_DATA_2(low_byte - 1));
+ RTL839X_TBL_ACCESS_DATA_2(low_byte - 1));
}
rtl839x_write_scheduling_table(port);
ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
for (int i = 0; i < 28; i += 8)
pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
- ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],
- ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);
+ ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],
+ ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);
pr_debug("CPU_PORT> %8x\n", ptr8[28]);
}
rtl_table_read(r, counter / 2);
pr_debug("Registers: %08x %08x\n",
- sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
+ sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
/* The table has a size of 2 registers */
if (counter % 2)
v = sw_r32(rtl_table_data(r, 0));
static void rtl838x_set_igr_filter(int port, enum igr_filter state)
{
- sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
+ sw_w32_mask(0x3 << ((port & 0xf) << 1), state << ((port & 0xf) << 1),
RTL838X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
}
ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
for (int i = 0; i < 52; i += 4)
pr_debug("> %16llx %16llx %16llx %16llx\n",
- ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
+ ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
}
pr_debug("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
pr_debug("Fixed : %06x\n", r[6] >> 8);
pr_debug("Match M: %08x %08x %08x %08x %08x %08x\n",
- (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
- (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
- (r[11] << 24) | (r[12] >> 8));
+ (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
+ (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
+ (r[11] << 24) | (r[12] >> 8));
pr_debug("R[13]: %08x\n", r[13]);
pr_debug("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
pr_debug("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
void rtl839x_pie_rule_dump(struct pie_rule *pr)
{
pr_debug("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
- pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
- pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
+ pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
+ pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
if (pr->fwd_sel)
pr_debug("FWD: %08x\n", pr->fwd_data);
pr_debug("TID: %x, %x\n", pr->tid, pr->tid_m);
static void rtl839x_set_igr_filter(int port, enum igr_filter state)
{
- sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
+ sw_w32_mask(0x3 << ((port & 0xf) << 1), state << ((port & 0xf) << 1),
RTL839X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
}
static void rtl839x_set_egr_filter(int port, enum egr_filter state)
{
sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20),
- RTL839X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2)));
+ RTL839X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2)));
}
static void rtl839x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
p[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 16) & 0x1FFFFFFF;
pr_debug("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x",
- profile, p[0] & (3 << 21), p[2], p[3], p[4]);
+ profile, p[0] & (3 << 21), p[2], p[3], p[4]);
pr_debug(" Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n",
- p[0] & BIT(17) ? 'y' : 'n', p[0] & BIT(16) ? 'y' : 'n',
- p[0] & BIT(13) ? 'y' : 'n', p[0] & BIT(12) ? 'y' : 'n');
+ p[0] & BIT(17) ? 'y' : 'n', p[0] & BIT(16) ? 'y' : 'n',
+ p[0] & BIT(13) ? 'y' : 'n', p[0] & BIT(12) ? 'y' : 'n');
pr_debug(" Bridge enabled: IPv4 MC %c, IPv6 MC %c,\n",
- p[0] & BIT(15) ? 'y' : 'n', p[0] & BIT(14) ? 'y' : 'n');
+ p[0] & BIT(15) ? 'y' : 'n', p[0] & BIT(14) ? 'y' : 'n');
pr_debug("VLAN profile %d: raw %08x %08x %08x %08x %08x\n",
- profile, p[0], p[1], p[2], p[3], p[4]);
+ profile, p[0], p[1], p[2], p[3], p[4]);
}
static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask)
pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos);
pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
- e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5]);
+ e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5]);
rtl930x_fill_l2_row(r, e);
for (int i = 0; i < 10; i++) {
pr_debug("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8,
- sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12),
- sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28));
+ sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12),
+ sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28));
r += 32;
}
pr_debug("# %08x %08x %08x %08x %08x\n",
- sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16));
+ sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16));
rtl930x_print_matrix();
pr_debug("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n",
- sw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL)
+ sw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL)
);
}
rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
if (rt->prefix_len < 0)
rt->prefix_len = find_last_bit((unsigned long *)&ip6_m.s6_addr32,
- 128);
+ 128);
break;
case 1: /* IPv4 Multicast route */
case 3: /* IPv6 Multicast route */
rt->attr.qos_prio = v & 0x7;
pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
- __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
- rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
+ __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
+ rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
out:
rtl_table_release(r);
rt->attr.qos_prio = v & 0x7;
pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
- __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
- rt->attr.dst_null);
+ __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
+ rt->attr.dst_null);
pr_debug("%s: Destination: %pI4\n", __func__, &rt->dst_ip);
out:
pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
- __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
- rt->attr.dst_null);
+ __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
+ rt->attr.dst_null);
pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
v = BIT(31); /* Entry is valid */
rtl930x_host_route_read(idx, &route_entry);
pr_debug("%s route valid %d, route dest: %pI4, hit %d\n", __func__,
- rt->attr.valid, &rt->dst_ip, rt->attr.hit);
+ rt->attr.valid, &rt->dst_ip, rt->attr.hit);
if (!must_exist && rt->attr.valid)
return idx;
if (must_exist && route_entry.dst_ip == rt->dst_ip)
pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
pr_debug("%s: nexthop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
- __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
- rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
+ __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
+ rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
v = rt->attr.valid ? BIT(31) : 0;
sw_w32(v, rtl_table_data(r, 10));
pr_debug("%s: %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n", __func__,
- sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
- sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
- sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)), sw_r32(rtl_table_data(r, 8)),
- sw_r32(rtl_table_data(r, 9)), sw_r32(rtl_table_data(r, 10)));
+ sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
+ sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
+ sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)), sw_r32(rtl_table_data(r, 8)),
+ sw_r32(rtl_table_data(r, 9)), sw_r32(rtl_table_data(r, 10)));
rtl_table_write(r, idx);
rtl_table_release(r);
struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
pr_debug("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n",
- __func__, idx, dmac_id, interface);
+ __func__, idx, dmac_id, interface);
sw_w32(((dmac_id & 0x7fff) << 7) | (interface & 0x7f), rtl_table_data(r, 0));
pr_debug("%s: %08x\n", __func__, sw_r32(rtl_table_data(r, 0)));
{
pr_debug("Raw IACL table entry:\n");
pr_debug("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
+ r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
pr_debug("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
+ r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
pr_debug("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
pr_debug("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
pr_debug("Fixed : %06x\n", r[6] >> 8);
pr_debug("Match M: %08x %08x %08x %08x %08x %08x\n",
- (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
- (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
- (r[11] << 24) | (r[12] >> 8));
+ (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
+ (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
+ (r[11] << 24) | (r[12] >> 8));
pr_debug("R[13]: %08x\n", r[13]);
pr_debug("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
pr_debug("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
t = (sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;
pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
pr_debug("%s: %08x\n",
- __func__, sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)));
+ __func__, sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)));
idx = rtl930x_pie_verify_template(priv, pr, t, block);
if (idx >= 0)
break;
sw_w32(m->action & 0x7, rtl_table_data(r, 6));
pr_debug("%s writing index %d: %08x %08x %08x %08x %08x %08x %08x\n", __func__, idx,
- sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
- sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
- sw_r32(rtl_table_data(r, 6))
+ sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
+ sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
+ sw_r32(rtl_table_data(r, 6))
);
rtl_table_write(r, idx);
rtl_table_release(r);
sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 1 = 1 */
pr_debug("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
- sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
- sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
+ sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
+ sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
sw_w32_mask(0, 1, RTL930X_L3_IPUC_ROUTE_CTRL);
sw_w32_mask(0, 1, RTL930X_L3_IP6UC_ROUTE_CTRL);
sw_w32_mask(0, 1, RTL930X_L3_IPMC_ROUTE_CTRL);
sw_w32(0x00012881, RTL930X_L3_IP6MC_ROUTE_CTRL);
pr_debug("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
- sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
- sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
+ sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
+ sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
/* Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable) */
sw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL);
rtl_table_read(r, counter / 2);
pr_debug("Registers: %08x %08x\n",
- sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
+ sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
/* The table has a size of 2 registers */
if (counter % 2)
v = sw_r32(rtl_table_data(r, 0));
else
info->l2_tunnel_list_id = -1;
pr_debug("%s read member %016llx, profile-id %d, uc %d, mc %d, intf-id %d\n", __func__,
- info->member_ports, info->profile_id, info->hash_uc_fid, info->hash_mc_fid,
- info->if_id);
+ info->member_ports, info->profile_id, info->hash_uc_fid, info->hash_mc_fid,
+ info->if_id);
/* Read UNTAG table via table register 3 */
r = rtl_table_get(RTL9310_TBL_3, 0);
pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos);
pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
- e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5]);
+ e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5]);
if (idx < 0x4000)
hash_algo_id = sw_r32(RTL931X_L2_CTRL) & BIT(0);
{
pr_debug("Raw IACL table entry:\n");
pr_debug("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
+ r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
pr_debug("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
+ r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
pr_debug("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
pr_debug("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
pr_debug("Fixed : %06x\n", r[6] >> 8);
pr_debug("Match M: %08x %08x %08x %08x %08x %08x\n",
- (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
- (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
- (r[11] << 24) | (r[12] >> 8));
+ (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
+ (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
+ (r[11] << 24) | (r[12] >> 8));
pr_debug("R[13]: %08x\n", r[13]);
pr_debug("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
pr_debug("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
pr_debug("%s: %08x\n",
- __func__, sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)));
+ __func__, sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)));
idx = rtl931x_pie_verify_template(priv, pr, t, block);
if (idx >= 0)
break;
/* Parse the flow rule for the matching conditions */
static int rtl83xx_parse_flow_rule(struct rtl838x_switch_priv *priv,
- struct flow_rule *rule, struct rtl83xx_flow *flow)
+ struct flow_rule *rule, struct rtl83xx_flow *flow)
{
struct flow_dissector *dissector = rule->match.dissector;
u32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts);
pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
- __func__, status_tx, status_rx, status_rx_r);
+ __func__, status_tx, status_rx, status_rx_r);
/* Ignore TX interrupt */
if (status_tx) {
struct ring_b *ring = priv->membase;
pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
- __func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN);
+ __func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN);
spin_lock_irqsave(&priv->lock, flags);
rtl838x_hw_reset(priv);
* so we do round-robin
*/
static u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
- struct net_device *sb_dev)
+ struct net_device *sb_dev)
{
static u8 last;
/* Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue
*/
static u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
- struct net_device *sb_dev)
+ struct net_device *sb_dev)
{
if (skb->priority >= TC_PRIO_CONTROL)
return 1;
if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {
if (&ring->rx_r[r][ring->c_rx[r]] != last) {
netdev_warn(dev, "Ring contention: r: %x, last %x, cur %x\n",
- r, (u32)last, (u32) &ring->rx_r[r][ring->c_rx[r]]);
+ r, (u32)last, (u32)&ring->rx_r[r][ring->c_rx[r]]);
}
break;
}
}
static void rtl838x_mac_link_up(struct phylink_config *config,
- struct phy_device *phy, unsigned int mode,
- phy_interface_t interface, int speed, int duplex,
- bool tx_pause, bool rx_pause)
+ struct phy_device *phy, unsigned int mode,
+ phy_interface_t interface, int speed, int duplex,
+ bool tx_pause, bool rx_pause)
{
struct net_device *dev = container_of(config->dev, struct net_device, dev);
struct rtl838x_eth_priv *priv = netdev_priv(dev);
}
static netdev_features_t rtl838x_fix_features(struct net_device *dev,
- netdev_features_t features)
+ netdev_features_t features)
{
return features;
}
struct ring_b *ring;
pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
- (u32)pdev, (u32)(&(pdev->dev)));
+ (u32)pdev, (u32)(&pdev->dev));
if (!dn) {
dev_err(&pdev->dev, "No DT found\n");
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res) {
mem = devm_request_mem_region(&pdev->dev, res->start,
- resource_size(res), res->name);
+ resource_size(res), res->name);
if (!mem) {
dev_err(&pdev->dev, "cannot request memory space\n");
return -ENXIO;
IRQF_SHARED, dev->name, dev);
if (err) {
dev_err(&pdev->dev, "%s: could not acquire interrupt: %d\n",
- __func__, err);
+ __func__, err);
return err;
}
netdev_warn(dev, "Failed to set MAC address.\n");
}
pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac),
- sw_r32(priv->r->mac + 4));
+ sw_r32(priv->r->mac + 4));
strscpy(dev->name, "eth%d", sizeof(dev->name));
priv->pdev = pdev;
*val = (*val & 0xffff0000) >> 16;
pr_debug("%s: port %d, page: %d, reg: %x, val: %x, v: %08x\n",
- __func__, port, page, reg, *val, v);
+ __func__, port, page, reg, *val, v);
mutex_unlock(&rtmdio_lock);
if (rtpcs_930x_sds_config_pll(ctrl, sds, interface))
pr_err("%s: SDS %d could not configure PLL for %s\n", __func__,
- sds, phy_modes(interface));
+ sds, phy_modes(interface));
rtpcs_930x_sds_set_internal_mode(ctrl, sds, mode);
if (rtpcs_930x_sds_wait_clock_ready(ctrl, sds))
val = rtpcs_sds_read_bits(ctrl, sds, 0x1F, 0x9, 11, 6);
pr_info("%s: fibermode %08X stored mode 0x%x", __func__,
- rtpcs_sds_read(ctrl, sds, 0x1f, 0x9), val);
+ rtpcs_sds_read(ctrl, sds, 0x1f, 0x9), val);
pr_info("%s: SGMII mode %08X in 0x24 0x9", __func__,
- rtpcs_sds_read(ctrl, sds, 0x24, 0x9));
+ rtpcs_sds_read(ctrl, sds, 0x24, 0x9));
pr_info("%s: CMU mode %08X stored even SDS %d", __func__,
- rtpcs_sds_read(ctrl, sds & ~1, 0x20, 0x12), sds & ~1);
+ rtpcs_sds_read(ctrl, sds & ~1, 0x20, 0x12), sds & ~1);
pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtpcs_sds_read(ctrl, sds, 0x24, 0x7));
pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtpcs_sds_read(ctrl, sds, 0x26, 0x7));
projects / openwrt / staging / stintel.git / commitdiff