[MIPS] vr41xx: Replace magic number for P4K bit with symbol.

Signed-off-by: Yoichi Yuasa <[email protected]>
Signed-off-by: Ralf Baechle <[email protected]>

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index d5111d165434bea0b88846642783208ad8fa4093..069803f58f3b2bb2c47676d49d574f15d45433cf 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -862,7 +862,7 @@ static void __init probe_pcache(void)
                break;
 
        case CPU_VR4133:
-               write_c0_config(config & ~CONF_EB);
+               write_c0_config(config & ~VR41_CONF_P4K);
        case CPU_VR4131:
                /* Workaround for cache instruction bug of VR4131 */
                if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||

diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 677668867b9d7ba057e9cfd3428f9f259305c8ce..1f318d7079983b378d1ee2a82ef3cf7eb378823c 100644 (file)
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -470,6 +470,7 @@
 
 /* Bits specific to the VR41xx.  */
 #define VR41_CONF_CS           (_ULCAST_(1) << 12)
+#define VR41_CONF_P4K          (_ULCAST_(1) << 13)
 #define VR41_CONF_BP           (_ULCAST_(1) << 16)
 #define VR41_CONF_M16          (_ULCAST_(1) << 20)
 #define VR41_CONF_AD           (_ULCAST_(1) << 23)