drm/amd/display: hide inconsistent mpcc programming from dtn log

Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 27ae88e3a3733b0772b33f706d9a493a488e34e4..e21458169d153e6a28d0d9d3ec3d2ae426206893 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -157,10 +157,11 @@ void dcn10_log_hw_state(struct dc *dc)
                struct mpcc_state s = {0};
 
                pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
-               DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  %12d  %4d\n",
-                       i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
-                       s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
-                       s.idle);
+               if (s.opp_id != 0xf)
+                       DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  %12d  %4d\n",
+                               i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
+                               s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
+                               s.idle);
        }
        DTN_INFO("\n");